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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim] - Rev 858

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858 orpsoc/tests: Fix or1200-dsxinsn when caches are not present

This test would go into an endless loop when caches are not present.
stekern 4118d 06h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
807 ORPSoC: Commit for bug 85 - add DSX support to OR1200.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85

Also added software tests, and added these tests to default regression test list
julius 4415d 21h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
805 ORPSoC: Fix for bug 90 - EPCR on range exception bug

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90
julius 4415d 21h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
803 ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91
julius 4415d 21h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
801 ORPSoC: Fix bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88
julius 4421d 02h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.
julius 4581d 21h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
671 ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model julius 4581d 22h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson
julius 4713d 23h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
535 ORPSoC - adding sw tests for l.rfe julius 4805d 02h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE
julius 4812d 10h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
506 ORPSoC or1200 interrupt and syscall generation test julius 4838d 05h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4855d 01h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default
julius 4858d 01h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4859d 22h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4893d 10h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.
julius 4913d 14h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4914d 10h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.
julius 4921d 13h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4953d 05h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 4959d 20h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...
julius 4972d 19h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.
julius 4972d 20h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4984d 19h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4986d 19h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4988d 01h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.
julius 4990d 06h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 4993d 05h /openrisc/trunk/orpsocv2/sw/tests/or1200/sim

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