Rev |
Log message |
Author |
Age |
Path |
493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4987d 14h |
/openrisc/trunk/orpsocv2 |
492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
4988d 12h |
/openrisc/trunk/orpsocv2 |
491 |
ORPSoC or1200_monitor update. |
julius |
4988d 23h |
/openrisc/trunk/orpsocv2 |
489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
4998d 11h |
/openrisc/trunk/orpsocv2 |
488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
4998d 12h |
/openrisc/trunk/orpsocv2 |
487 |
ORPSoC main software makefile update |
julius |
5001d 10h |
/openrisc/trunk/orpsocv2 |
486 |
ORPSoC updates, mainly software, i2c driver |
julius |
5001d 10h |
/openrisc/trunk/orpsocv2 |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
5005d 14h |
/openrisc/trunk/orpsocv2 |
480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
5022d 19h |
/openrisc/trunk/orpsocv2 |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
5023d 18h |
/openrisc/trunk/orpsocv2 |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
5025d 10h |
/openrisc/trunk/orpsocv2 |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
5025d 18h |
/openrisc/trunk/orpsocv2 |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
5026d 11h |
/openrisc/trunk/orpsocv2 |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
5026d 14h |
/openrisc/trunk/orpsocv2 |
470 |
ORPSoC OR1200 crt0 updates. |
julius |
5030d 14h |
/openrisc/trunk/orpsocv2 |
468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
5031d 15h |
/openrisc/trunk/orpsocv2 |
466 |
ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README |
julius |
5032d 18h |
/openrisc/trunk/orpsocv2 |
465 |
ORPSoC SPI flash load Makefile and README updates. |
julius |
5033d 08h |
/openrisc/trunk/orpsocv2 |
462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
5033d 17h |
/openrisc/trunk/orpsocv2 |
456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
5045d 10h |
/openrisc/trunk/orpsocv2 |
449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
5058d 05h |
/openrisc/trunk/orpsocv2 |
439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
5065d 09h |
/openrisc/trunk/orpsocv2 |
435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
5072d 00h |
/openrisc/trunk/orpsocv2 |
431 |
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC S/W and makefile updates. |
julius |
5078d 07h |
/openrisc/trunk/orpsocv2 |
426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
5084d 23h |
/openrisc/trunk/orpsocv2 |
425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
5085d 00h |
/openrisc/trunk/orpsocv2 |
417 |
ORPSoC re-adding doc automake files, this time not symlinks |
julius |
5093d 09h |
/openrisc/trunk/orpsocv2 |
416 |
ORPSoC doc cleanup - removing symlinks from automake'd docs build path |
julius |
5093d 09h |
/openrisc/trunk/orpsocv2 |
415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
5093d 09h |
/openrisc/trunk/orpsocv2 |
412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
5096d 23h |
/openrisc/trunk/orpsocv2 |