OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc] - Rev 196

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
196 Fixed name for newlib install option. jeremybennett 5145d 19h /openrisc
195 Adding linux and uClibc paths back for patches, updated gnu-src build script making newlib an option (off by deafult) julius 5145d 19h /openrisc
194 Tidied up code setjmp and longjmp into their own files, and adjusted Makefile accordingly. Simplified cache setup in startup code. Replaced calls via register with calls using immediate address. jeremybennett 5146d 13h /openrisc
193 Record changes to initfini.c jeremybennett 5146d 13h /openrisc
192 Updated to fix problems with initfini assembler fragments. jeremybennett 5146d 13h /openrisc
191 Updated to clarify use of r9 in the l.jalr delay slot. jeremybennett 5146d 13h /openrisc
190 Allow the Or1ksim installation directory to be set by option. jeremybennett 5146d 19h /openrisc
189 Fuller explanation of the build script given. jeremybennett 5146d 19h /openrisc
188 More rigorous testing of options. jeremybennett 5146d 20h /openrisc
187 Or1200 sprs FPU update julius 5148d 13h /openrisc
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5148d 16h /openrisc
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5148d 17h /openrisc
184 Fix the UART version of newlib. jeremybennett 5149d 21h /openrisc
183 Fix to setjmp, so it works. Some commenting tidy ups elsewhere. jeremybennett 5150d 13h /openrisc
182 Removed redundant code. jeremybennett 5150d 13h /openrisc
181 Updated, so only GCC tries to use parallel build. Redundant target for libgcc removed. jeremybennett 5150d 15h /openrisc
180 Rewritten to use namespace clean BSP in libgloss. Two versions of the library, one with, one without using the UART. jeremybennett 5150d 15h /openrisc
179 Code is now loaded from address 0, with section .vectors loaded before any other section. This provides a convenient mechanism for setting up the OR1K exception vectors. jeremybennett 5150d 15h /openrisc
178 Fixes a bug in prologue recognition without frame pointer. jeremybennett 5150d 15h /openrisc
177 Specified CPU type for or32, corrected templates for or32-*-elf*. Corrected specs in or32.h, added init and fini. Added support for newlib, including -mor32-newlib and -mor32-newlib-uart options. jeremybennett 5150d 16h /openrisc
176 Removing empty and redundant directory. jeremybennett 5155d 17h /openrisc
175 Moved orpmon into bootloaders julius 5155d 17h /openrisc
174 Consolidating all RTOS ports in one directory. jeremybennett 5155d 18h /openrisc
173 Consolidating all RTOS ports in one directory. jeremybennett 5155d 18h /openrisc
172 Information about this directory. jeremybennett 5155d 18h /openrisc
171 A new directory for ports of real time operating systems. jeremybennett 5155d 18h /openrisc
170 More detailed instructions. jeremybennett 5155d 19h /openrisc
169 Script to build entire tool chain and library from unified source tree. jeremybennett 5155d 19h /openrisc
168 Removing, since all relevant content has been moved to the unified GNU source and patches directories. jeremybennett 5155d 19h /openrisc
167 Moving to unified patches directory. jeremybennett 5155d 19h /openrisc

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.