Rev |
Log message |
Author |
Age |
Path |
801 |
ORPSoC: Fix bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4469d 19h |
/openrisc |
800 |
FreeRTOSV6.1.1
add or32_dma demo task for test dcache manuplation function
add simple driver of wb_dma |
filepang |
4482d 10h |
/openrisc |
799 |
FreeRTOSV6.1.1
add cache related function from u-boot from OpenRISC
enable I/D cache if present |
filepang |
4483d 10h |
/openrisc |
798 |
Added drivers for ethmac and sdcard_mass_storage_controller |
skrzyp |
4485d 19h |
/openrisc |
797 |
testsuite: kill test processes that timeout |
pgavin |
4494d 00h |
/openrisc |
796 |
Correct orpmon show_rx_buffs and show_mac_regs to use TX_BD_NUM properly. |
yannv |
4497d 03h |
/openrisc |
795 |
Created or1200_rel3 branch from rev 794 |
olof |
4497d 18h |
/openrisc |
794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4503d 04h |
/openrisc |
793 |
Corrected Julius Baxter's email address in MAINTAINERS |
jeremybennett |
4514d 03h |
/openrisc |
792 |
Added a MAINTAINERS file.
012-04-07 Jeremy Bennett <jeremy.bennett@embecosm.com>
* MAINTAINERS: Added.
* configure: Regenerated.
* configure.ac: Updated version. |
jeremybennett |
4514d 03h |
/openrisc |
791 |
Added options to configure RAM and ROM sizes. Fixed cache handling. |
skrzyp |
4516d 22h |
/openrisc |
790 |
fixed issues with context switching, interrupts, optimizations and cleanups |
skrzyp |
4523d 22h |
/openrisc |
789 |
ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4527d 17h |
/openrisc |
788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4527d 18h |
/openrisc |
787 |
Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:
2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version. |
jeremybennett |
4529d 02h |
/openrisc |
786 |
new ecos tree (tracking mainline) |
skrzyp |
4529d 02h |
/openrisc |
785 |
We are about to upload a new tree (that has a different structure) |
skrzyp |
4529d 03h |
/openrisc |
784 |
Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.
2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour. |
jeremybennett |
4530d 17h |
/openrisc |
783 |
Initial dev directory snapshot with FSF GCC mainline |
jeremybennett |
4544d 16h |
/openrisc |
782 |
Tags directory for GNU development tool chain. |
jeremybennett |
4544d 16h |
/openrisc |
781 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4547d 03h |
/openrisc |
780 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4549d 17h |
/openrisc |
779 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4549d 17h |
/openrisc |
778 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4549d 17h |
/openrisc |
777 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4549d 17h |
/openrisc |
776 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4549d 17h |
/openrisc |
775 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4549d 17h |
/openrisc |
774 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4549d 17h |
/openrisc |
773 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4549d 17h |
/openrisc |
772 |
Initial check-in of GCC, with properties matching the upstream. |
jeremybennett |
4549d 17h |
/openrisc |