Rev |
Log message |
Author |
Age |
Path |
58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5369d 09h |
/openrisc |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5374d 13h |
/openrisc |
56 |
adding generic pll model to orpsoc |
julius |
5382d 15h |
/openrisc |
55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5385d 05h |
/openrisc |
54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5395d 12h |
/openrisc |
53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5413d 13h |
/openrisc |
52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5414d 09h |
/openrisc |
51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5428d 11h |
/openrisc |
50 |
Adding or32_funcs.S |
julius |
5428d 15h |
/openrisc |
49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5447d 05h |
/openrisc |
48 |
Adds an initialization to keep GCC happy in jp1_ll_read_jp1. |
jeremybennett |
5447d 08h |
/openrisc |
47 |
debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions |
julius |
5456d 16h |
/openrisc |
46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5462d 16h |
/openrisc |
45 |
Orpsoc eth test fix and script error message update |
julius |
5469d 16h |
/openrisc |
44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5498d 16h |
/openrisc |
43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5522d 13h |
/openrisc |
42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5538d 09h |
/openrisc |
41 |
Update to or1k top |
julius |
5541d 11h |
/openrisc |
40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5542d 16h |
/openrisc |
39 |
Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update |
julius |
5546d 16h |
/openrisc |
38 |
Adding binutils, gcc, uClibc patched source and patches |
julius |
5556d 16h |
/openrisc |
37 |
Update to the toolchain script - uses gcc-core package now instead of complete gcc |
julius |
5556d 17h |
/openrisc |
36 |
Better clean rule in makefile |
julius |
5556d 17h |
/openrisc |
35 |
Download and patch files with README files updated to explain what is in the new repository |
jeremybennett |
5557d 10h |
/openrisc |
34 |
Created directories for download and patch files and added README's explaining what is in each one. |
jeremybennett |
5557d 10h |
/openrisc |
33 |
version 2.1 of GDB 6.8 for the OpenRISC architecture |
jeremybennett |
5557d 11h |
/openrisc |
32 |
Tags directory for versions of GDB 6.8 |
jeremybennett |
5557d 11h |
/openrisc |
31 |
Tags directory for all GDB versions |
jeremybennett |
5557d 11h |
/openrisc |
30 |
copied rtems from or1k repo |
unneback |
5557d 12h |
/openrisc |
29 |
|
unneback |
5557d 13h |
/openrisc |