OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_45] - Rev 1022

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8015d 21h /or1k/tags/nog_patch_45
1021 *** empty log message *** rherveille 8020d 00h /or1k/tags/nog_patch_45
1020 Fixed several bugs
Working version, tested on Bender hardware
rherveille 8020d 00h /or1k/tags/nog_patch_45
1019 fixed some bugs detected by Bender hardware rherveille 8020d 00h /or1k/tags/nog_patch_45
1018 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8020d 07h /or1k/tags/nog_patch_45
1017 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8020d 07h /or1k/tags/nog_patch_45
1016 64 bytes is the smallest packet size. simons 8020d 23h /or1k/tags/nog_patch_45
1015 Host type was not recognized. simons 8021d 09h /or1k/tags/nog_patch_45
1014 added _JBLEN definition for or1k ivang 8021d 23h /or1k/tags/nog_patch_45
1013 ORP architecture supported. simons 8022d 01h /or1k/tags/nog_patch_45
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8022d 18h /or1k/tags/nog_patch_45
1010 Import ivang 8026d 21h /or1k/tags/nog_patch_45
1009 Import ivang 8026d 21h /or1k/tags/nog_patch_45
1008 Import ivang 8026d 22h /or1k/tags/nog_patch_45
1007 Import ivang 8026d 22h /or1k/tags/nog_patch_45
1006 Import ivang 8026d 22h /or1k/tags/nog_patch_45
1005 Import ivang 8026d 22h /or1k/tags/nog_patch_45
1004 Now every ramdisk image should have init program. simons 8027d 07h /or1k/tags/nog_patch_45
1003 cuc temporary files are deleted upon exiting markom 8027d 07h /or1k/tags/nog_patch_45
1002 Now every ramdisk image should have init program. simons 8027d 07h /or1k/tags/nog_patch_45
1001 fixed load/store state machine verilog generation errors markom 8027d 07h /or1k/tags/nog_patch_45
1000 IC/DC cache enable routines fixed. simons 8027d 07h /or1k/tags/nog_patch_45
999 Now every ramdisk image should have init program. simons 8027d 08h /or1k/tags/nog_patch_45
998 added missing fout initialization markom 8027d 10h /or1k/tags/nog_patch_45
997 PRINTF should be used instead of printf; command redirection repaired markom 8027d 11h /or1k/tags/nog_patch_45
996 some minor bugs fixed markom 8028d 10h /or1k/tags/nog_patch_45
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8028d 17h /or1k/tags/nog_patch_45
993 Fixed IMMU bug. lampret 8028d 17h /or1k/tags/nog_patch_45
992 A bug when cache enabled and bus error comes fixed. simons 8029d 02h /or1k/tags/nog_patch_45
991 Different memory controller. simons 8029d 02h /or1k/tags/nog_patch_45

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.