OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [cache/] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5596d 01h /or1k/tags/nog_patch_52/or1ksim/cache
1429 This commit was manufactured by cvs2svn to create tag 'nog_patch_52'. 7036d 08h /or1k/tags/nog_patch_52/or1ksim/cache
1406 Fix the declaration of `sec' in reg_ic_sec nogj 7036d 08h /or1k/tags/nog_patch_52/or1ksim/cache
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7036d 08h /or1k/tags/nog_patch_52/or1ksim/cache
1402 Do what dc_clock() did in mtspr() and remove it nogj 7036d 08h /or1k/tags/nog_patch_52/or1ksim/cache
1386 Rework exception handling nogj 7042d 11h /or1k/tags/nog_patch_52/or1ksim/cache
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.
nogj 7051d 12h /or1k/tags/nog_patch_52/or1ksim/cache
1376 aclocal && autoconf && automake phoenix 7070d 12h /or1k/tags/nog_patch_52/or1ksim/cache
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7077d 03h /or1k/tags/nog_patch_52/or1ksim/cache
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7086d 06h /or1k/tags/nog_patch_52/or1ksim/cache
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7099d 10h /or1k/tags/nog_patch_52/or1ksim/cache
1308 Gyorgy Jeney: extensive cleanup phoenix 7291d 00h /or1k/tags/nog_patch_52/or1ksim/cache
1249 Downgrading back to automake-1.4 lampret 7456d 00h /or1k/tags/nog_patch_52/or1ksim/cache
1117 Ignore generated files for CVS purposes sfurman 7799d 01h /or1k/tags/nog_patch_52/or1ksim/cache
1099 cvs bug fixed markom 7885d 12h /or1k/tags/nog_patch_52/or1ksim/cache
1085 Bug fixed. simons 7898d 02h /or1k/tags/nog_patch_52/or1ksim/cache
997 PRINTF should be used instead of printf; command redirection repaired markom 7987d 15h /or1k/tags/nog_patch_52/or1ksim/cache
992 A bug when cache enabled and bus error comes fixed. simons 7989d 06h /or1k/tags/nog_patch_52/or1ksim/cache
970 Testbench is now running on ORP architecture platform. simons 7995d 02h /or1k/tags/nog_patch_52/or1ksim/cache
884 code cleaning - a lot of global variables moved to runtime struct markom 8031d 13h /or1k/tags/nog_patch_52/or1ksim/cache
876 Beta release of ATA simulation rherveille 8039d 01h /or1k/tags/nog_patch_52/or1ksim/cache
638 TLBTR CI bit is now working properly. simons 8190d 03h /or1k/tags/nog_patch_52/or1ksim/cache
631 Real cache access is simulated now. simons 8193d 01h /or1k/tags/nog_patch_52/or1ksim/cache
626 store buffer added markom 8193d 15h /or1k/tags/nog_patch_52/or1ksim/cache
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8214d 10h /or1k/tags/nog_patch_52/or1ksim/cache
517 some performance optimizations markom 8218d 10h /or1k/tags/nog_patch_52/or1ksim/cache
500 Added .cvsignore files for annoying generated files erez 8220d 13h /or1k/tags/nog_patch_52/or1ksim/cache
429 cache configuration added markom 8242d 09h /or1k/tags/nog_patch_52/or1ksim/cache
428 cache configuration added markom 8242d 09h /or1k/tags/nog_patch_52/or1ksim/cache
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8281d 14h /or1k/tags/nog_patch_52/or1ksim/cache

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.