OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_58/] [or1ksim] - Rev 82

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
82 Changed pctemp to pcnext. lampret 8506d 01h /or1k/tags/nog_patch_58/or1ksim
79 Data and instruction cache simulation added. lampret 8535d 17h /or1k/tags/nog_patch_58/or1ksim
78 (i/d)tlb_status lampret 8659d 07h /or1k/tags/nog_patch_58/or1ksim
77 Regular update. lampret 8659d 07h /or1k/tags/nog_patch_58/or1ksim
76 regular update lampret 8659d 07h /or1k/tags/nog_patch_58/or1ksim
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8659d 07h /or1k/tags/nog_patch_58/or1ksim
74 Same as DMMU. lampret 8666d 06h /or1k/tags/nog_patch_58/or1ksim
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8666d 06h /or1k/tags/nog_patch_58/or1ksim
72 Added 'how to build GNU tools' lampret 8671d 07h /or1k/tags/nog_patch_58/or1ksim
69 Sim debug. lampret 8678d 07h /or1k/tags/nog_patch_58/or1ksim
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8678d 07h /or1k/tags/nog_patch_58/or1ksim
67 Added simulator "application load". lampret 8678d 07h /or1k/tags/nog_patch_58/or1ksim
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.
lampret 8678d 07h /or1k/tags/nog_patch_58/or1ksim
65 Added DMMU stats. lampret 8678d 07h /or1k/tags/nog_patch_58/or1ksim
64 SPR bit definition moved to spr_defs.h. lampret 8678d 07h /or1k/tags/nog_patch_58/or1ksim
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).
lampret 8678d 07h /or1k/tags/nog_patch_58/or1ksim
62 OR1K DMMU model. lampret 8678d 07h /or1k/tags/nog_patch_58/or1ksim
60 Memory model changed. lampret 8713d 10h /or1k/tags/nog_patch_58/or1ksim
55 Added 'dv' command for dumping memory as verilog model. lampret 8729d 07h /or1k/tags/nog_patch_58/or1ksim
54 Regular maintenance. lampret 8729d 07h /or1k/tags/nog_patch_58/or1ksim
52 Comment character changed. lampret 8790d 03h /or1k/tags/nog_patch_58/or1ksim
51 Exception detection changed a bit. lampret 8790d 03h /or1k/tags/nog_patch_58/or1ksim
50 Added CURINSN macro. lampret 8790d 03h /or1k/tags/nog_patch_58/or1ksim
49 Changed simulation mode to non-virtual (real). lampret 8790d 03h /or1k/tags/nog_patch_58/or1ksim
48 Added CCR. lampret 8790d 03h /or1k/tags/nog_patch_58/or1ksim
47 Added interrupt recognition and better memory dump. lampret 8790d 03h /or1k/tags/nog_patch_58/or1ksim
46 Added srand(). lampret 8790d 03h /or1k/tags/nog_patch_58/or1ksim
45 Added NONE. lampret 8790d 03h /or1k/tags/nog_patch_58/or1ksim
44 %s bug fixed. lampret 8795d 08h /or1k/tags/nog_patch_58/or1ksim
43 SUPV bit from SR is now saved into EPCR bit 0. lampret 8800d 11h /or1k/tags/nog_patch_58/or1ksim

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.