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[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [mmu/] [dmmu.c] - Rev 1382

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1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7047d 19h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7073d 10h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7082d 13h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7095d 17h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7287d 07h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
1240 additional functions to bypass cache and mmu needed for peripheral devices phoenix 7459d 02h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7983d 22h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
886 MMU registers reserved fields protected from writing. simons 8027d 14h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8027d 20h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
638 TLBTR CI bit is now working properly. simons 8186d 10h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8199d 08h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
572 Some new bugs fixed. simons 8204d 09h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8210d 18h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
535 stats is updated; statical single stats removed; t command output cleaned, added time output; cycles is moved to instructions; cycles now count time markom 8211d 16h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
456 Page size bug fixed. simons 8235d 12h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
438 ITLB -> DTLB lapsus fixed. simons 8237d 16h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
430 dpfault and ipfault exceptions implemented markom 8238d 15h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
429 cache configuration added markom 8238d 16h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
425 immu and dmmu configurations added markom 8238d 18h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8265d 19h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8363d 16h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8446d 02h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8652d 23h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
62 OR1K DMMU model. lampret 8664d 23h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8887d 09h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c

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