OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_62] - Rev 1167

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1167 Corrected offset of TSS field within task_struct. csanchez 7690d 19h /or1k/tags/nog_patch_62
1166 Fixed problem with relocations of non-allocated sections. csanchez 7690d 19h /or1k/tags/nog_patch_62
1165 timeout bug fixed; contribution by Carlos markom 7707d 13h /or1k/tags/nog_patch_62
1161 When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. lampret 7711d 02h /or1k/tags/nog_patch_62
1160 added missing .rodata.* section into rom linker script phoenix 7742d 02h /or1k/tags/nog_patch_62
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7754d 05h /or1k/tags/nog_patch_62
1158 Added simple uart test case. lampret 7755d 06h /or1k/tags/nog_patch_62
1157 Added syscall test case. lampret 7755d 07h /or1k/tags/nog_patch_62
1156 Tick timer test case added. lampret 7756d 03h /or1k/tags/nog_patch_62
1155 No functional change. Only added customization for exception vectors. lampret 7757d 06h /or1k/tags/nog_patch_62
1154 When using tty channel, put the serial port into raw mode (no echo, no
CR/LF conversion, no other line discipline/buffering).
sfurman 7764d 22h /or1k/tags/nog_patch_62
1153 When multiple interrupts were pending, e.g. TX buffer empty and RX
available, reading the UART's IIR register could potentially clear a
TX interrupt before it had been sent to the processor, thus dropping
the interrupt permanently.

Fix tested w/ both eCos and uclinux.
sfurman 7765d 08h /or1k/tags/nog_patch_62
1152 *** empty log message *** phoenix 7765d 12h /or1k/tags/nog_patch_62
1151 *** empty log message *** phoenix 7765d 12h /or1k/tags/nog_patch_62
1150 remove unneded include phoenix 7765d 14h /or1k/tags/nog_patch_62
1149 *** empty log message *** phoenix 7766d 01h /or1k/tags/nog_patch_62
1148 *** empty log message *** phoenix 7766d 02h /or1k/tags/nog_patch_62
1147 remove unneeded include phoenix 7766d 02h /or1k/tags/nog_patch_62
1146 cygwin fix phoenix 7766d 02h /or1k/tags/nog_patch_62
1145 1) Fix trivial bug w/ transmitter empty interrupts that I introduced in the
last check-in.
2) Improve printed output from debugging-only uart_status() routine.
sfurman 7766d 02h /or1k/tags/nog_patch_62
1144 Speed up gdb when running with serial targets:

When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)

When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump.
sfurman 7768d 08h /or1k/tags/nog_patch_62
1143 Make UART transmitter-empty interrupts match both 16450 and 16550 behavior. sfurman 7768d 23h /or1k/tags/nog_patch_62
1142 Speed up gdb when running with serial targets:

When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)

When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump.
sfurman 7768d 23h /or1k/tags/nog_patch_62
1141 WB = 1/2 RISC clock test code enabled. lampret 7770d 08h /or1k/tags/nog_patch_62
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7770d 08h /or1k/tags/nog_patch_62
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7770d 08h /or1k/tags/nog_patch_62
1138 Added some information how to run simulations. lampret 7771d 03h /or1k/tags/nog_patch_62
1137 Added RFRAM generic and Altera lpm library. lampret 7771d 03h /or1k/tags/nog_patch_62
1136 Add altera lpm library. lampret 7771d 03h /or1k/tags/nog_patch_62
1135 Added get_gpr support for OR1200_RFRAM_GENERIC lampret 7771d 03h /or1k/tags/nog_patch_62

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.