OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_62] - Rev 1200

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1200 mbist signals updated according to newest convention markom 7607d 07h /or1k/tags/nog_patch_62
1199 Daniel Wiklund: Removed multiple entries of debug/Makefile in configure danwi 7611d 08h /or1k/tags/nog_patch_62
1198 make it compile on RH 8,9 phoenix 7636d 23h /or1k/tags/nog_patch_62
1197 disabled ram-init of ps2 (old) +
changed MAC type into DOS type, so that Xilinx ISE can work with it
dries 7642d 04h /or1k/tags/nog_patch_62
1196 removed second debug/Makefile (credits: Daniel Wiklund - danwi@isy.liu.se) dries 7642d 05h /or1k/tags/nog_patch_62
1195 made the project file a little bit more universal dries 7642d 06h /or1k/tags/nog_patch_62
1194 correct all the syntax errors dries 7642d 06h /or1k/tags/nog_patch_62
1193 disabled SRAM_GENERIC and added comment +
corrected 'wb_err' into 'wb_err_o'
dries 7642d 06h /or1k/tags/nog_patch_62
1192 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
dries 7642d 08h /or1k/tags/nog_patch_62
1191 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
dries 7642d 08h /or1k/tags/nog_patch_62
1188 Added support for rams with byte write access. simons 7658d 07h /or1k/tags/nog_patch_62
1186 Added support for rams with byte write access. simons 7659d 06h /or1k/tags/nog_patch_62
1184 Scan signals mess fixed. simons 7665d 23h /or1k/tags/nog_patch_62
1183 OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0 sfurman 7670d 14h /or1k/tags/nog_patch_62
1181 Initial import of unmodified gdb-5.3 source on vendor branch sfurman 7670d 16h /or1k/tags/nog_patch_62
1179 BIST interface added for Artisan memory instances. simons 7674d 02h /or1k/tags/nog_patch_62
1178 avoid another immu exception that should not happen phoenix 7703d 13h /or1k/tags/nog_patch_62
1177 more informative output phoenix 7704d 20h /or1k/tags/nog_patch_62
1176 Added comments. damonb 7705d 11h /or1k/tags/nog_patch_62
1174 fix for immu exceptions that never should have happened phoenix 7706d 15h /or1k/tags/nog_patch_62
1170 Added support for l.addc instruction. csanchez 7714d 19h /or1k/tags/nog_patch_62
1169 Added support for l.addc instruction. csanchez 7714d 20h /or1k/tags/nog_patch_62
1168 Added explicit alignment expressions. csanchez 7720d 06h /or1k/tags/nog_patch_62
1167 Corrected offset of TSS field within task_struct. csanchez 7720d 06h /or1k/tags/nog_patch_62
1166 Fixed problem with relocations of non-allocated sections. csanchez 7720d 06h /or1k/tags/nog_patch_62
1165 timeout bug fixed; contribution by Carlos markom 7737d 00h /or1k/tags/nog_patch_62
1161 When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. lampret 7740d 12h /or1k/tags/nog_patch_62
1160 added missing .rodata.* section into rom linker script phoenix 7771d 13h /or1k/tags/nog_patch_62
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7783d 15h /or1k/tags/nog_patch_62
1158 Added simple uart test case. lampret 7784d 17h /or1k/tags/nog_patch_62

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.