OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_62] - Rev 802

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
802 Cache and tick timer tests fixed. simons 8136d 22h /or1k/tags/nog_patch_62
801 l.muli instruction added markom 8138d 18h /or1k/tags/nog_patch_62
800 Bug fixed. simons 8139d 16h /or1k/tags/nog_patch_62
799 Wrapping around 512k boundary to simulate real hw. simons 8143d 09h /or1k/tags/nog_patch_62
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8143d 09h /or1k/tags/nog_patch_62
797 Changed hardcoded address for fake MC to use a define. lampret 8143d 10h /or1k/tags/nog_patch_62
796 Removed unused ports wb_clki and wb_rst_i lampret 8143d 10h /or1k/tags/nog_patch_62
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8143d 15h /or1k/tags/nog_patch_62
794 Added again just recently removed full_case directive lampret 8143d 15h /or1k/tags/nog_patch_62
793 Added synthesis off/on for timescale.v included file. lampret 8143d 15h /or1k/tags/nog_patch_62
792 Fixed port names that changed. lampret 8143d 15h /or1k/tags/nog_patch_62
791 Fixed some ports in instnatiations that were removed from the modules lampret 8143d 15h /or1k/tags/nog_patch_62
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8143d 15h /or1k/tags/nog_patch_62
789 Added response from memory controller (addr 0x60000000) lampret 8143d 16h /or1k/tags/nog_patch_62
788 Some of the warnings fixed. lampret 8143d 16h /or1k/tags/nog_patch_62
787 Added romfs.tgz lampret 8144d 10h /or1k/tags/nog_patch_62
786 Moved UCF constraint file to the backend directory. lampret 8144d 10h /or1k/tags/nog_patch_62
785 Added XSV specific documentation. lampret 8144d 11h /or1k/tags/nog_patch_62
784 Added soem missing files. lampret 8144d 11h /or1k/tags/nog_patch_62
783 Added sim directory and sub files/dirs. lampret 8144d 11h /or1k/tags/nog_patch_62
782 Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory. lampret 8144d 11h /or1k/tags/nog_patch_62
781 Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well. lampret 8144d 11h /or1k/tags/nog_patch_62
780 Added libraries. lampret 8144d 11h /or1k/tags/nog_patch_62
779 Added bench directory lampret 8144d 11h /or1k/tags/nog_patch_62
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8144d 12h /or1k/tags/nog_patch_62
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8144d 12h /or1k/tags/nog_patch_62
776 Updated defines. lampret 8144d 12h /or1k/tags/nog_patch_62
775 Optimized cache controller FSM. lampret 8144d 12h /or1k/tags/nog_patch_62
774 Removed old files. lampret 8144d 13h /or1k/tags/nog_patch_62
773 Changing directory structure ... lampret 8144d 13h /or1k/tags/nog_patch_62

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.