OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_68/] [gen_or1k_isa/] [sources/] [opcode/] [or32.c] - Rev 1778

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5602d 16h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1462 This commit was manufactured by cvs2svn to create tag 'nog_patch_68'. 7042d 22h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1452 Implement a dynamic recompiler to speed up the execution nogj 7042d 22h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1440 Reclasify l.trap and l.sys to be an exception instruction nogj 7042d 23h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1384 Fix the parameters to the l.ff1/l.maci instructions nogj 7058d 02h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7092d 21h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1346 Remove the global op structure nogj 7106d 00h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.		 nogj 7106d 01h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1341 Mark wich operand is the destination operand in the architechture definition nogj 7106d 01h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1338 l.ff1 instruction added andreje 7121d 23h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1309 removed includes phoenix 7294d 18h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7297d 16h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1295 Updated instruction set descriptions. Changed FP instructions encoding. lampret 7319d 16h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1286 Changed desciption of the l.cust5 insns lampret 7368d 19h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1285 Changed desciption of the l.cust5 insns lampret 7368d 19h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1169 Added support for l.addc instruction. csanchez 7681d 19h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1114 Added cvs log keywords lampret 7836d 11h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
1034 Fixed encoding for l.div/l.divu. lampret 7978d 12h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
879 Initial version of OpenRISC Custom Unit Compiler added markom 8043d 22h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
801 l.muli instruction added markom 8136d 01h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
722 floating point registers are obsolete; GPRs should be used instead markom 8164d 01h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
720 single floating point support added markom 8164d 05h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
717 some minor improvements markom 8164d 07h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
714 do_stats introduced for faster no-stats execution markom 8166d 02h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
709 eval_operands is now being generated markom 8169d 08h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
706 insn_decode execution part replaced by generated function decode_execute; use --enable-simple to use runtime decoding markom 8170d 01h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
703 small optimizations to dissasemble markom 8171d 05h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
676 update of shared files markom 8183d 01h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
671 wrong version was restored markom 8183d 06h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c
662 GNU binutils merge. ivang 8187d 03h /or1k/tags/nog_patch_68/gen_or1k_isa/sources/opcode/or32.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.