| Rev |
Log message |
Author |
Age |
Path |
| 1765 |
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root |
5600d 09h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1749 |
This commit was manufactured by cvs2svn to create tag 'rel-0-3-0-rc1'. |
|
5749d 14h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1748 |
These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.
Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals. |
jeremybennett |
5749d 14h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1715 |
Add the capability to the pic to simulate a level or edge triggered pic. Add
a clear_interrupt() function that the peripherals need to use to signal that
they negated their interrupt line. |
nogj |
6746d 11h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1652 |
Avoid division and multiplication as far as possible (they are slow) |
nogj |
6746d 13h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1579 |
Add missing break; statements |
nogj |
6858d 21h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1557 |
Fix most warnings issued by gcc4 |
nogj |
6882d 23h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1551 |
Remove the pcprev global |
nogj |
6944d 12h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1550 |
* prototype() -> prototype(void) where appropriate.
* Use `static' where it can be used. |
nogj |
6944d 12h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1549 |
Spelling fixes |
nogj |
6944d 12h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1540 |
* Breakup the tick_job function into smaller ones.
* Fix lots of conner cases.
* Add tests for the tick timer. |
nogj |
6944d 12h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1532 |
Add pretty spr dumping code |
nogj |
6948d 12h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1531 |
Remove non-trigerable out-of-range checks |
nogj |
6948d 12h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1529 |
* The effective address as written to the I/DCBPR registers needs to be translated by the respective mmu.
* Don't treat any values as special in the handling of DCPBR, DCBFR, DCBIR, ICBPR and ICBIR. |
nogj |
6949d 14h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1513 |
Remove the flag global |
nogj |
6949d 20h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1508 |
Remove m{f,t}spr calls where we can access the spr directly |
nogj |
6949d 20h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1486 |
* Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity. |
nogj |
6992d 21h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1471 |
Rewrite the interactive mode handling to also work in the recompiler |
nogj |
7040d 16h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1452 |
Implement a dynamic recompiler to speed up the execution |
nogj |
7040d 16h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1446 |
Cosmetic fixes |
nogj |
7040d 16h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1432 |
Collect most of the cpu state variables in a structure (cpu_state) |
nogj |
7040d 16h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1404 |
Move the function of ic_clock() to mtspr() and remove it |
nogj |
7040d 16h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1402 |
Do what dc_clock() did in mtspr() and remove it |
nogj |
7040d 16h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1386 |
Rework exception handling |
nogj |
7046d 20h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1354 |
typing fixes |
phoenix |
7089d 17h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1350 |
Mark a simulated cpu address as such, by introducing the new oraddr_t type |
nogj |
7090d 14h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1308 |
Gyorgy Jeney: extensive cleanup |
phoenix |
7295d 09h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1302 |
compile fix (remove const) |
phoenix |
7313d 07h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1203 |
value stored in ITLB and DTLB match registers was wrong. fixed. |
phoenix |
7547d 04h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
| 1106 |
Cache invalidate bug fixed again (it was ok before). |
simons |
7883d 16h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or1k/sprs.c |
