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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog] - Rev 573

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Rev Log message Author Age Path
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8215d 01h /or1k/tags/rel_1/or1200/rtl/verilog
571 Changed alignment exception EPCR. Not tested yet. lampret 8215d 10h /or1k/tags/rel_1/or1200/rtl/verilog
570 Fixed order of syscall and range exceptions. lampret 8215d 12h /or1k/tags/rel_1/or1200/rtl/verilog
569 Default ASIC configuration does not sample WB inputs. lampret 8215d 22h /or1k/tags/rel_1/or1200/rtl/verilog
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8216d 01h /or1k/tags/rel_1/or1200/rtl/verilog
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8222d 07h /or1k/tags/rel_1/or1200/rtl/verilog
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8226d 10h /or1k/tags/rel_1/or1200/rtl/verilog
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8226d 23h /or1k/tags/rel_1/or1200/rtl/verilog
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8257d 02h /or1k/tags/rel_1/or1200/rtl/verilog
401 *** empty log message *** simons 8260d 13h /or1k/tags/rel_1/or1200/rtl/verilog
400 force_dslot_fetch does not work - allways zero. simons 8260d 13h /or1k/tags/rel_1/or1200/rtl/verilog
399 Trap insn couses break after exits ex_insn. simons 8260d 13h /or1k/tags/rel_1/or1200/rtl/verilog
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8263d 08h /or1k/tags/rel_1/or1200/rtl/verilog
390 Changed instantiation name of VS RAMs. lampret 8263d 10h /or1k/tags/rel_1/or1200/rtl/verilog
387 Now FPGA and ASIC target are separate. lampret 8263d 12h /or1k/tags/rel_1/or1200/rtl/verilog
386 Fixed VS RAM instantiation - again. lampret 8263d 12h /or1k/tags/rel_1/or1200/rtl/verilog
370 Program counter divided to PPC and NPC. simons 8267d 10h /or1k/tags/rel_1/or1200/rtl/verilog
367 Changed DSR/DRR behavior and exception detection. lampret 8267d 23h /or1k/tags/rel_1/or1200/rtl/verilog
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8268d 18h /or1k/tags/rel_1/or1200/rtl/verilog
360 Added OR1200_REGISTERED_INPUTS. lampret 8270d 10h /or1k/tags/rel_1/or1200/rtl/verilog
359 Added optional sampling of inputs. lampret 8270d 10h /or1k/tags/rel_1/or1200/rtl/verilog
358 Fixed virtual silicon single-port rams instantiation. lampret 8270d 10h /or1k/tags/rel_1/or1200/rtl/verilog
357 Fixed dbg_is_o assignment width. lampret 8270d 10h /or1k/tags/rel_1/or1200/rtl/verilog
356 Break point bug fixed simons 8270d 13h /or1k/tags/rel_1/or1200/rtl/verilog
354 Fixed width of du_except. lampret 8271d 07h /or1k/tags/rel_1/or1200/rtl/verilog
353 Cashes disabled. simons 8271d 17h /or1k/tags/rel_1/or1200/rtl/verilog
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8272d 20h /or1k/tags/rel_1/or1200/rtl/verilog
351 Fixed some l.trap typos. lampret 8272d 22h /or1k/tags/rel_1/or1200/rtl/verilog
350 For GDB changed single stepping and disabled trap exception. lampret 8272d 23h /or1k/tags/rel_1/or1200/rtl/verilog
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8277d 21h /or1k/tags/rel_1/or1200/rtl/verilog

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