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[/] [or1k/] [tags/] [rel_10/] - Rev 987

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Rev Log message Author Age Path
987 ORP architecture supported. simons 8001d 05h /or1k/tags/rel_10
986 outputs out of function are not registered anymore markom 8001d 06h /or1k/tags/rel_10
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8001d 17h /or1k/tags/rel_10
984 Disable SB until it is tested lampret 8001d 18h /or1k/tags/rel_10
983 First checkin lampret 8001d 20h /or1k/tags/rel_10
982 Moved to sim/bin lampret 8001d 20h /or1k/tags/rel_10
981 First checkin. lampret 8001d 20h /or1k/tags/rel_10
980 Removed sim.tcl that shouldn't be here. lampret 8001d 20h /or1k/tags/rel_10
979 Removed old test case binaries. lampret 8001d 20h /or1k/tags/rel_10
978 Added variable delay for SRAM. lampret 8001d 20h /or1k/tags/rel_10
977 Added store buffer. lampret 8001d 20h /or1k/tags/rel_10
976 Added store buffer lampret 8001d 20h /or1k/tags/rel_10
975 First checkin lampret 8001d 20h /or1k/tags/rel_10
974 Enabled what works on or1ksim and disabled other tests. lampret 8001d 22h /or1k/tags/rel_10
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8004d 02h /or1k/tags/rel_10
972 Interrupt suorces fixed. simons 8004d 02h /or1k/tags/rel_10
971 Now even keyboard test passes. simons 8004d 05h /or1k/tags/rel_10
970 Testbench is now running on ORP architecture platform. simons 8004d 18h /or1k/tags/rel_10
969 Checking in except directory. lampret 8005d 09h /or1k/tags/rel_10
968 Checking in utils directory. lampret 8005d 09h /or1k/tags/rel_10
967 Checking in mul directory. lampret 8005d 09h /or1k/tags/rel_10
966 Checking in cbasic directory. lampret 8005d 09h /or1k/tags/rel_10
965 Checking in basic directory. lampret 8005d 09h /or1k/tags/rel_10
964 Checking in support directory. lampret 8005d 09h /or1k/tags/rel_10
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8005d 10h /or1k/tags/rel_10
961 uart16550 RTL files renamed/added/removed. lampret 8005d 10h /or1k/tags/rel_10
960 Directory cleanup. lampret 8005d 10h /or1k/tags/rel_10
959 Fixed size of generic flash/sram to exactly 2MB lampret 8006d 09h /or1k/tags/rel_10
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8006d 09h /or1k/tags/rel_10
957 Flash at 0x04000000 RAM at 0x00000000. Only MMU test works. simons 8006d 19h /or1k/tags/rel_10

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