OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_10] - Rev 1024

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1024 Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes. simons 8013d 12h /or1k/tags/rel_10
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8013d 23h /or1k/tags/rel_10
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8014d 01h /or1k/tags/rel_10
1021 *** empty log message *** rherveille 8018d 04h /or1k/tags/rel_10
1020 Fixed several bugs
Working version, tested on Bender hardware
rherveille 8018d 04h /or1k/tags/rel_10
1019 fixed some bugs detected by Bender hardware rherveille 8018d 04h /or1k/tags/rel_10
1018 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8018d 10h /or1k/tags/rel_10
1017 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8018d 11h /or1k/tags/rel_10
1016 64 bytes is the smallest packet size. simons 8019d 03h /or1k/tags/rel_10
1015 Host type was not recognized. simons 8019d 13h /or1k/tags/rel_10
1014 added _JBLEN definition for or1k ivang 8020d 02h /or1k/tags/rel_10
1013 ORP architecture supported. simons 8020d 05h /or1k/tags/rel_10
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8020d 22h /or1k/tags/rel_10
1010 Import ivang 8025d 01h /or1k/tags/rel_10
1009 Import ivang 8025d 01h /or1k/tags/rel_10
1008 Import ivang 8025d 02h /or1k/tags/rel_10
1007 Import ivang 8025d 02h /or1k/tags/rel_10
1006 Import ivang 8025d 02h /or1k/tags/rel_10
1005 Import ivang 8025d 02h /or1k/tags/rel_10
1004 Now every ramdisk image should have init program. simons 8025d 10h /or1k/tags/rel_10
1003 cuc temporary files are deleted upon exiting markom 8025d 10h /or1k/tags/rel_10
1002 Now every ramdisk image should have init program. simons 8025d 11h /or1k/tags/rel_10
1001 fixed load/store state machine verilog generation errors markom 8025d 11h /or1k/tags/rel_10
1000 IC/DC cache enable routines fixed. simons 8025d 11h /or1k/tags/rel_10
999 Now every ramdisk image should have init program. simons 8025d 12h /or1k/tags/rel_10
998 added missing fout initialization markom 8025d 14h /or1k/tags/rel_10
997 PRINTF should be used instead of printf; command redirection repaired markom 8025d 15h /or1k/tags/rel_10
996 some minor bugs fixed markom 8026d 13h /or1k/tags/rel_10
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8026d 21h /or1k/tags/rel_10
993 Fixed IMMU bug. lampret 8026d 21h /or1k/tags/rel_10

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.