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[/] [or1k/] [tags/] [rel_12/] [or1200] - Rev 597

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Rev Log message Author Age Path
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8240d 13h /or1k/tags/rel_12/or1200
596 SR[TEE] should be zero after reset. lampret 8240d 18h /or1k/tags/rel_12/or1200
595 Fixed 'the NPC single-step fix'. lampret 8241d 13h /or1k/tags/rel_12/or1200
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8241d 20h /or1k/tags/rel_12/or1200
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8244d 21h /or1k/tags/rel_12/or1200
571 Changed alignment exception EPCR. Not tested yet. lampret 8245d 06h /or1k/tags/rel_12/or1200
570 Fixed order of syscall and range exceptions. lampret 8245d 08h /or1k/tags/rel_12/or1200
569 Default ASIC configuration does not sample WB inputs. lampret 8245d 18h /or1k/tags/rel_12/or1200
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8245d 21h /or1k/tags/rel_12/or1200
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8252d 03h /or1k/tags/rel_12/or1200
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8256d 06h /or1k/tags/rel_12/or1200
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8256d 19h /or1k/tags/rel_12/or1200
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8286d 23h /or1k/tags/rel_12/or1200
401 *** empty log message *** simons 8290d 09h /or1k/tags/rel_12/or1200
400 force_dslot_fetch does not work - allways zero. simons 8290d 09h /or1k/tags/rel_12/or1200
399 Trap insn couses break after exits ex_insn. simons 8290d 09h /or1k/tags/rel_12/or1200
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8293d 04h /or1k/tags/rel_12/or1200
390 Changed instantiation name of VS RAMs. lampret 8293d 06h /or1k/tags/rel_12/or1200
387 Now FPGA and ASIC target are separate. lampret 8293d 08h /or1k/tags/rel_12/or1200
386 Fixed VS RAM instantiation - again. lampret 8293d 08h /or1k/tags/rel_12/or1200
370 Program counter divided to PPC and NPC. simons 8297d 06h /or1k/tags/rel_12/or1200
367 Changed DSR/DRR behavior and exception detection. lampret 8297d 19h /or1k/tags/rel_12/or1200
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8298d 14h /or1k/tags/rel_12/or1200
360 Added OR1200_REGISTERED_INPUTS. lampret 8300d 06h /or1k/tags/rel_12/or1200
359 Added optional sampling of inputs. lampret 8300d 06h /or1k/tags/rel_12/or1200
358 Fixed virtual silicon single-port rams instantiation. lampret 8300d 06h /or1k/tags/rel_12/or1200
357 Fixed dbg_is_o assignment width. lampret 8300d 06h /or1k/tags/rel_12/or1200
356 Break point bug fixed simons 8300d 09h /or1k/tags/rel_12/or1200
354 Fixed width of du_except. lampret 8301d 03h /or1k/tags/rel_12/or1200
353 Cashes disabled. simons 8301d 13h /or1k/tags/rel_12/or1200

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