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[/] [or1k/] [tags/] [rel_12] - Rev 802

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Rev Log message Author Age Path
802 Cache and tick timer tests fixed. simons 8137d 20h /or1k/tags/rel_12
801 l.muli instruction added markom 8139d 16h /or1k/tags/rel_12
800 Bug fixed. simons 8140d 14h /or1k/tags/rel_12
799 Wrapping around 512k boundary to simulate real hw. simons 8144d 07h /or1k/tags/rel_12
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8144d 07h /or1k/tags/rel_12
797 Changed hardcoded address for fake MC to use a define. lampret 8144d 08h /or1k/tags/rel_12
796 Removed unused ports wb_clki and wb_rst_i lampret 8144d 08h /or1k/tags/rel_12
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8144d 12h /or1k/tags/rel_12
794 Added again just recently removed full_case directive lampret 8144d 13h /or1k/tags/rel_12
793 Added synthesis off/on for timescale.v included file. lampret 8144d 13h /or1k/tags/rel_12
792 Fixed port names that changed. lampret 8144d 13h /or1k/tags/rel_12
791 Fixed some ports in instnatiations that were removed from the modules lampret 8144d 13h /or1k/tags/rel_12
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8144d 13h /or1k/tags/rel_12
789 Added response from memory controller (addr 0x60000000) lampret 8144d 13h /or1k/tags/rel_12
788 Some of the warnings fixed. lampret 8144d 14h /or1k/tags/rel_12
787 Added romfs.tgz lampret 8145d 08h /or1k/tags/rel_12
786 Moved UCF constraint file to the backend directory. lampret 8145d 08h /or1k/tags/rel_12
785 Added XSV specific documentation. lampret 8145d 08h /or1k/tags/rel_12
784 Added soem missing files. lampret 8145d 08h /or1k/tags/rel_12
783 Added sim directory and sub files/dirs. lampret 8145d 08h /or1k/tags/rel_12
782 Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory. lampret 8145d 09h /or1k/tags/rel_12
781 Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well. lampret 8145d 09h /or1k/tags/rel_12
780 Added libraries. lampret 8145d 09h /or1k/tags/rel_12
779 Added bench directory lampret 8145d 09h /or1k/tags/rel_12
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8145d 10h /or1k/tags/rel_12
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8145d 10h /or1k/tags/rel_12
776 Updated defines. lampret 8145d 10h /or1k/tags/rel_12
775 Optimized cache controller FSM. lampret 8145d 10h /or1k/tags/rel_12
774 Removed old files. lampret 8145d 10h /or1k/tags/rel_12
773 Changing directory structure ... lampret 8145d 11h /or1k/tags/rel_12

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