OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_12] - Rev 812

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
812 new number parsing, ip parsing markom 8131d 12h /or1k/tags/rel_12
810 This commit was generated by cvs2svn to compensate for changes in r809,
which included commits to RCS files with non-trunk default branches.		 simons 8131d 15h /or1k/tags/rel_12
808 Elf support added. simons 8131d 16h /or1k/tags/rel_12
807 sched files moved to support dir markom 8132d 18h /or1k/tags/rel_12
806 uart now partially uses scheduler markom 8132d 18h /or1k/tags/rel_12
805 kbd, fb, vga devices now uses scheduler markom 8132d 19h /or1k/tags/rel_12
804 memory regions can now overlap with MC -- not according to MC spec markom 8133d 13h /or1k/tags/rel_12
803 Free irq handler fixed. simons 8136d 06h /or1k/tags/rel_12
802 Cache and tick timer tests fixed. simons 8137d 17h /or1k/tags/rel_12
801 l.muli instruction added markom 8139d 13h /or1k/tags/rel_12
800 Bug fixed. simons 8140d 11h /or1k/tags/rel_12
799 Wrapping around 512k boundary to simulate real hw. simons 8144d 04h /or1k/tags/rel_12
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8144d 04h /or1k/tags/rel_12
797 Changed hardcoded address for fake MC to use a define. lampret 8144d 05h /or1k/tags/rel_12
796 Removed unused ports wb_clki and wb_rst_i lampret 8144d 05h /or1k/tags/rel_12
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8144d 09h /or1k/tags/rel_12
794 Added again just recently removed full_case directive lampret 8144d 09h /or1k/tags/rel_12
793 Added synthesis off/on for timescale.v included file. lampret 8144d 09h /or1k/tags/rel_12
792 Fixed port names that changed. lampret 8144d 09h /or1k/tags/rel_12
791 Fixed some ports in instnatiations that were removed from the modules lampret 8144d 09h /or1k/tags/rel_12
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8144d 10h /or1k/tags/rel_12
789 Added response from memory controller (addr 0x60000000) lampret 8144d 10h /or1k/tags/rel_12
788 Some of the warnings fixed. lampret 8144d 11h /or1k/tags/rel_12
787 Added romfs.tgz lampret 8145d 05h /or1k/tags/rel_12
786 Moved UCF constraint file to the backend directory. lampret 8145d 05h /or1k/tags/rel_12
785 Added XSV specific documentation. lampret 8145d 05h /or1k/tags/rel_12
784 Added soem missing files. lampret 8145d 05h /or1k/tags/rel_12
783 Added sim directory and sub files/dirs. lampret 8145d 05h /or1k/tags/rel_12
782 Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory. lampret 8145d 05h /or1k/tags/rel_12
781 Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well. lampret 8145d 06h /or1k/tags/rel_12

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.