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[/] [or1k/] [tags/] [rel_16/] [or1200] - Rev 1131

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1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7801d 02h /or1k/tags/rel_16/or1200
1130 RFRAM type always need to be defined. lampret 7801d 02h /or1k/tags/rel_16/or1200
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7801d 02h /or1k/tags/rel_16/or1200
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7876d 00h /or1k/tags/rel_16/or1200
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7920d 18h /or1k/tags/rel_16/or1200
1083 SB mem width fixed. simons 7952d 13h /or1k/tags/rel_16/or1200
1079 RAMs wrong connected to the BIST scan chain. mohor 7961d 11h /or1k/tags/rel_16/or1200
1078 Previous check-in was done by mistake. mohor 7961d 12h /or1k/tags/rel_16/or1200
1077 Signal scanb_sen renamed to scanb_en. mohor 7961d 12h /or1k/tags/rel_16/or1200
1069 Signal scanb_eni renamed to scanb_en mohor 7965d 05h /or1k/tags/rel_16/or1200
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7972d 07h /or1k/tags/rel_16/or1200
1055 Removed obsolete comment. lampret 8004d 00h /or1k/tags/rel_16/or1200
1054 Fixed a combinational loop. lampret 8004d 00h /or1k/tags/rel_16/or1200
1053 Disabled cache inhibit atttribute. lampret 8004d 00h /or1k/tags/rel_16/or1200
1040 Updated the script. lampret 8011d 06h /or1k/tags/rel_16/or1200
1039 Added linter directory. lampret 8011d 06h /or1k/tags/rel_16/or1200
1038 Fixed a typo, reported by Taylor Su. lampret 8011d 08h /or1k/tags/rel_16/or1200
1037 First import of the new synopsys DC scripts. lampret 8011d 09h /or1k/tags/rel_16/or1200
1036 Removed old synthesis scripts. lampret 8011d 09h /or1k/tags/rel_16/or1200
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 8011d 21h /or1k/tags/rel_16/or1200
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 8012d 08h /or1k/tags/rel_16/or1200
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8012d 22h /or1k/tags/rel_16/or1200
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8016d 03h /or1k/tags/rel_16/or1200
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8016d 05h /or1k/tags/rel_16/or1200
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8023d 02h /or1k/tags/rel_16/or1200
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8029d 01h /or1k/tags/rel_16/or1200
993 Fixed IMMU bug. lampret 8029d 01h /or1k/tags/rel_16/or1200
984 Disable SB until it is tested lampret 8032d 05h /or1k/tags/rel_16/or1200
977 Added store buffer. lampret 8032d 07h /or1k/tags/rel_16/or1200
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8035d 21h /or1k/tags/rel_16/or1200

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