OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_16] - Rev 636

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
636 Fixed combinational loops. lampret 8201d 03h /or1k/tags/rel_16
635 Fixed Makefile bug. ivang 8201d 05h /or1k/tags/rel_16
634 configure.in : fixed to build start/Makefile
start.S : l.jalr r9 -> l.jr r9

Added missing files.		 ivang 8202d 06h /or1k/tags/rel_16
633 Bug fix in command line parser. ivang 8202d 07h /or1k/tags/rel_16
632 profiler and mprofiler merged into sim. ivang 8203d 02h /or1k/tags/rel_16
631 Real cache access is simulated now. simons 8204d 01h /or1k/tags/rel_16
630 some bug fixes in store buffer analysis markom 8204d 10h /or1k/tags/rel_16
629 typo fixed markom 8204d 13h /or1k/tags/rel_16
627 or32 restored markom 8204d 14h /or1k/tags/rel_16
626 store buffer added markom 8204d 14h /or1k/tags/rel_16
625 Bus error bug fixed. Cache routines added. simons 8205d 06h /or1k/tags/rel_16
624 Added logging of writes/read to/from SPR registers. ivang 8205d 07h /or1k/tags/rel_16
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8205d 09h /or1k/tags/rel_16
622 Cache test works on hardware. simons 8205d 12h /or1k/tags/rel_16
621 Cache test works on hardware. simons 8205d 13h /or1k/tags/rel_16
620 use ARITH_SET_FLAG to turn off set flag by arith. instructions markom 8205d 13h /or1k/tags/rel_16
619 all test pass, after newest changes markom 8205d 13h /or1k/tags/rel_16
618 Fixed display of new 'void' nop insns. lampret 8205d 22h /or1k/tags/rel_16
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8205d 22h /or1k/tags/rel_16
616 flags test added markom 8208d 08h /or1k/tags/rel_16
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8208d 08h /or1k/tags/rel_16
614 Changed to support new debug if. simons 8208d 15h /or1k/tags/rel_16
613 init: trap exception occurs always; initialization of sr not needed anymore markom 8209d 12h /or1k/tags/rel_16
612 Tick timer period extended to meet real timing. simons 8209d 14h /or1k/tags/rel_16
611 EEAR register is not changed by trap, sys, int, tick and range exception. simons 8210d 15h /or1k/tags/rel_16
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8210d 15h /or1k/tags/rel_16
609 Added wb_err_o to flash and sram i/f for testing the buserr exception. lampret 8210d 15h /or1k/tags/rel_16
608 Range exception removed from test. simons 8211d 11h /or1k/tags/rel_16
607 single step steps just one instruction ^c bug fixed markom 8211d 11h /or1k/tags/rel_16
606 raw register range bug fixed; acv_uart test passes markom 8212d 11h /or1k/tags/rel_16

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.