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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog] - Rev 1210

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Rev Log message Author Age Path
1210 No functional change. lampret 7554d 12h /or1k/tags/rel_21/or1200/rtl/verilog
1209 Fixed instantiation name. lampret 7554d 12h /or1k/tags/rel_21/or1200/rtl/verilog
1207 Static exception prefix. lampret 7554d 12h /or1k/tags/rel_21/or1200/rtl/verilog
1206 Static exception prefix. lampret 7554d 13h /or1k/tags/rel_21/or1200/rtl/verilog
1175 Added three missing wire declarations. No functional changes. lampret 7701d 11h /or1k/tags/rel_21/or1200/rtl/verilog
1172 Added embedded memory QMEM. lampret 7703d 21h /or1k/tags/rel_21/or1200/rtl/verilog
1171 Added embedded memory QMEM. lampret 7703d 21h /or1k/tags/rel_21/or1200/rtl/verilog
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7736d 10h /or1k/tags/rel_21/or1200/rtl/verilog
1161 When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. lampret 7736d 10h /or1k/tags/rel_21/or1200/rtl/verilog
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7779d 12h /or1k/tags/rel_21/or1200/rtl/verilog
1155 No functional change. Only added customization for exception vectors. lampret 7782d 14h /or1k/tags/rel_21/or1200/rtl/verilog
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7795d 16h /or1k/tags/rel_21/or1200/rtl/verilog
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7795d 16h /or1k/tags/rel_21/or1200/rtl/verilog
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7796d 11h /or1k/tags/rel_21/or1200/rtl/verilog
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7796d 11h /or1k/tags/rel_21/or1200/rtl/verilog
1130 RFRAM type always need to be defined. lampret 7796d 11h /or1k/tags/rel_21/or1200/rtl/verilog
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7796d 11h /or1k/tags/rel_21/or1200/rtl/verilog
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7871d 09h /or1k/tags/rel_21/or1200/rtl/verilog
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7916d 03h /or1k/tags/rel_21/or1200/rtl/verilog
1083 SB mem width fixed. simons 7947d 23h /or1k/tags/rel_21/or1200/rtl/verilog
1079 RAMs wrong connected to the BIST scan chain. mohor 7956d 20h /or1k/tags/rel_21/or1200/rtl/verilog
1078 Previous check-in was done by mistake. mohor 7956d 21h /or1k/tags/rel_21/or1200/rtl/verilog
1077 Signal scanb_sen renamed to scanb_en. mohor 7956d 21h /or1k/tags/rel_21/or1200/rtl/verilog
1069 Signal scanb_eni renamed to scanb_en mohor 7960d 14h /or1k/tags/rel_21/or1200/rtl/verilog
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7967d 16h /or1k/tags/rel_21/or1200/rtl/verilog
1055 Removed obsolete comment. lampret 7999d 09h /or1k/tags/rel_21/or1200/rtl/verilog
1054 Fixed a combinational loop. lampret 7999d 09h /or1k/tags/rel_21/or1200/rtl/verilog
1053 Disabled cache inhibit atttribute. lampret 7999d 09h /or1k/tags/rel_21/or1200/rtl/verilog
1038 Fixed a typo, reported by Taylor Su. lampret 8006d 17h /or1k/tags/rel_21/or1200/rtl/verilog
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 8007d 07h /or1k/tags/rel_21/or1200/rtl/verilog

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