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[/] [or1k/] [tags/] [rel_21/] [or1200] - Rev 775

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Rev Log message Author Age Path
775 Optimized cache controller FSM. lampret 8145d 02h /or1k/tags/rel_21/or1200
774 Removed old files. lampret 8145d 02h /or1k/tags/rel_21/or1200
737 Added alternative for critical path in DU. lampret 8159d 21h /or1k/tags/rel_21/or1200
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8162d 20h /or1k/tags/rel_21/or1200
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8162d 20h /or1k/tags/rel_21/or1200
668 Lapsus fixed. simons 8187d 06h /or1k/tags/rel_21/or1200
663 No longer using async rst as sync reset for the counter. lampret 8189d 20h /or1k/tags/rel_21/or1200
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8190d 17h /or1k/tags/rel_21/or1200
636 Fixed combinational loops. lampret 8200d 01h /or1k/tags/rel_21/or1200
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8204d 20h /or1k/tags/rel_21/or1200
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8209d 13h /or1k/tags/rel_21/or1200
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8213d 07h /or1k/tags/rel_21/or1200
596 SR[TEE] should be zero after reset. lampret 8213d 12h /or1k/tags/rel_21/or1200
595 Fixed 'the NPC single-step fix'. lampret 8214d 07h /or1k/tags/rel_21/or1200
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8214d 13h /or1k/tags/rel_21/or1200
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8217d 15h /or1k/tags/rel_21/or1200
571 Changed alignment exception EPCR. Not tested yet. lampret 8218d 00h /or1k/tags/rel_21/or1200
570 Fixed order of syscall and range exceptions. lampret 8218d 02h /or1k/tags/rel_21/or1200
569 Default ASIC configuration does not sample WB inputs. lampret 8218d 11h /or1k/tags/rel_21/or1200
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8218d 15h /or1k/tags/rel_21/or1200
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8224d 20h /or1k/tags/rel_21/or1200
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8229d 00h /or1k/tags/rel_21/or1200
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8229d 13h /or1k/tags/rel_21/or1200
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8259d 16h /or1k/tags/rel_21/or1200
401 *** empty log message *** simons 8263d 02h /or1k/tags/rel_21/or1200
400 force_dslot_fetch does not work - allways zero. simons 8263d 02h /or1k/tags/rel_21/or1200
399 Trap insn couses break after exits ex_insn. simons 8263d 02h /or1k/tags/rel_21/or1200
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8265d 22h /or1k/tags/rel_21/or1200
390 Changed instantiation name of VS RAMs. lampret 8266d 00h /or1k/tags/rel_21/or1200
387 Now FPGA and ASIC target are separate. lampret 8266d 01h /or1k/tags/rel_21/or1200

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