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[/] [or1k/] [tags/] [rel_21] - Rev 208

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Rev Log message Author Age Path
208 Initial checkin with working port to or1k chris 8327d 09h /or1k/tags/rel_21
207 Several major changes to allow gdb to work with an Or1k implementation
that does not need a writeable PC. This version will use the breakpoint
vector and install a new vector into the EPC register, and then single
step out of the breakpoint exception. The breakpoint exception vector
must include only 2 commands: l.rfe and l.nop. Anything else and this
gdb version will fail w/ or1ksim.		 chris 8327d 13h /or1k/tags/rel_21
206 Several modifications to support gdb in a new exception style mode.
This new version works with gdb, and does not require the simulator
to implement a writeable PC.		 chris 8327d 13h /or1k/tags/rel_21
205 Adding debug capabilities. Half done. lampret 8331d 16h /or1k/tags/rel_21
204 Added function prototypes to stop gcc from complaining erez 8334d 08h /or1k/tags/rel_21
203 Updated from xess branch. lampret 8335d 21h /or1k/tags/rel_21
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf		 erez 8341d 05h /or1k/tags/rel_21
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8341d 05h /or1k/tags/rel_21
200 Initial import simons 8344d 12h /or1k/tags/rel_21
199 Initial import simons 8344d 14h /or1k/tags/rel_21
198 Moved from testbench.old simons 8347d 00h /or1k/tags/rel_21
197 This is not used any more. simons 8347d 01h /or1k/tags/rel_21
196 Configuration SPRs added. simons 8347d 01h /or1k/tags/rel_21
195 New test added. simons 8347d 01h /or1k/tags/rel_21
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.		 chris 8347d 09h /or1k/tags/rel_21
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8347d 09h /or1k/tags/rel_21
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.		 chris 8347d 18h /or1k/tags/rel_21
191 Added UART jitter var to sim config chris 8348d 15h /or1k/tags/rel_21
190 Added jitter initialization chris 8348d 15h /or1k/tags/rel_21
189 fixed mode handling for tick facility chris 8348d 15h /or1k/tags/rel_21
188 fixed PIC interrupt controller chris 8348d 15h /or1k/tags/rel_21
187 minor change to clear pending exception chris 8348d 15h /or1k/tags/rel_21
186 major change to UART structure chris 8348d 15h /or1k/tags/rel_21
185 major change to UART code chris 8348d 15h /or1k/tags/rel_21
184 modified decode for trace debugging chris 8348d 15h /or1k/tags/rel_21
183 changed special case for PICSR chris 8348d 15h /or1k/tags/rel_21
182 updated exception handling procedures chris 8348d 15h /or1k/tags/rel_21
181 Added trace/stall commands chris 8348d 15h /or1k/tags/rel_21
180 Updated debug. lampret 8348d 21h /or1k/tags/rel_21
179 Sim run script lampret 8368d 13h /or1k/tags/rel_21

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