OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_24] - Rev 211

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
211 Added check for "long long" erez 8349d 01h /or1k/tags/rel_24
210 Updated debug. More cleanup. Added MAC. lampret 8352d 07h /or1k/tags/rel_24
209 Update debug. lampret 8354d 12h /or1k/tags/rel_24
208 Initial checkin with working port to or1k chris 8355d 23h /or1k/tags/rel_24
207 Several major changes to allow gdb to work with an Or1k implementation
that does not need a writeable PC. This version will use the breakpoint
vector and install a new vector into the EPC register, and then single
step out of the breakpoint exception. The breakpoint exception vector
must include only 2 commands: l.rfe and l.nop. Anything else and this
gdb version will fail w/ or1ksim.		 chris 8356d 03h /or1k/tags/rel_24
206 Several modifications to support gdb in a new exception style mode.
This new version works with gdb, and does not require the simulator
to implement a writeable PC.		 chris 8356d 03h /or1k/tags/rel_24
205 Adding debug capabilities. Half done. lampret 8360d 06h /or1k/tags/rel_24
204 Added function prototypes to stop gcc from complaining erez 8362d 22h /or1k/tags/rel_24
203 Updated from xess branch. lampret 8364d 11h /or1k/tags/rel_24
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf		 erez 8369d 19h /or1k/tags/rel_24
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8369d 19h /or1k/tags/rel_24
200 Initial import simons 8373d 02h /or1k/tags/rel_24
199 Initial import simons 8373d 03h /or1k/tags/rel_24
198 Moved from testbench.old simons 8375d 14h /or1k/tags/rel_24
197 This is not used any more. simons 8375d 14h /or1k/tags/rel_24
196 Configuration SPRs added. simons 8375d 15h /or1k/tags/rel_24
195 New test added. simons 8375d 15h /or1k/tags/rel_24
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.		 chris 8375d 23h /or1k/tags/rel_24
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8375d 23h /or1k/tags/rel_24
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.		 chris 8376d 08h /or1k/tags/rel_24
191 Added UART jitter var to sim config chris 8377d 05h /or1k/tags/rel_24
190 Added jitter initialization chris 8377d 05h /or1k/tags/rel_24
189 fixed mode handling for tick facility chris 8377d 05h /or1k/tags/rel_24
188 fixed PIC interrupt controller chris 8377d 05h /or1k/tags/rel_24
187 minor change to clear pending exception chris 8377d 05h /or1k/tags/rel_24
186 major change to UART structure chris 8377d 05h /or1k/tags/rel_24
185 major change to UART code chris 8377d 05h /or1k/tags/rel_24
184 modified decode for trace debugging chris 8377d 05h /or1k/tags/rel_24
183 changed special case for PICSR chris 8377d 05h /or1k/tags/rel_24
182 updated exception handling procedures chris 8377d 05h /or1k/tags/rel_24

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.