OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_24] - Rev 78

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
78 (i/d)tlb_status lampret 8689d 15h /or1k/tags/rel_24
77 Regular update. lampret 8689d 16h /or1k/tags/rel_24
76 regular update lampret 8689d 16h /or1k/tags/rel_24
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8689d 16h /or1k/tags/rel_24
74 Same as DMMU. lampret 8696d 15h /or1k/tags/rel_24
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8696d 15h /or1k/tags/rel_24
72 Added 'how to build GNU tools' lampret 8701d 16h /or1k/tags/rel_24
71 Clean two typos. lampret 8706d 17h /or1k/tags/rel_24
70 Basic setjmp/longjmp are ready. lampret 8706d 18h /or1k/tags/rel_24
69 Sim debug. lampret 8708d 15h /or1k/tags/rel_24
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8708d 15h /or1k/tags/rel_24
67 Added simulator "application load". lampret 8708d 15h /or1k/tags/rel_24
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.		 lampret 8708d 15h /or1k/tags/rel_24
65 Added DMMU stats. lampret 8708d 15h /or1k/tags/rel_24
64 SPR bit definition moved to spr_defs.h. lampret 8708d 15h /or1k/tags/rel_24
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).		 lampret 8708d 15h /or1k/tags/rel_24
62 OR1K DMMU model. lampret 8708d 16h /or1k/tags/rel_24
61 2000-09-26 Joel Sherrill <joel@OARcorp.com>

* libc/sys/rtems/include/pthread.h: Added file missed by earlier
commit of RTEMS modifications.		 joel 8723d 10h /or1k/tags/rel_24
60 Memory model changed. lampret 8743d 19h /or1k/tags/rel_24
59 2000-09-05 Joel Sherrill <joel@OARcorp.com>

* Merged newlib-1.8.2-rtems-20000905.diff which includes
or16 and or32 configuration support.		 joel 8744d 06h /or1k/tags/rel_24
57 This commit was generated by cvs2svn to compensate for changes in r56, which
included commits to RCS files with non-trunk default branches.		 joel 8750d 04h /or1k/tags/rel_24
55 Added 'dv' command for dumping memory as verilog model. lampret 8759d 16h /or1k/tags/rel_24
54 Regular maintenance. lampret 8759d 16h /or1k/tags/rel_24
53 Added setjmp/longjmp. lampret 8764d 16h /or1k/tags/rel_24
52 Comment character changed. lampret 8820d 11h /or1k/tags/rel_24
51 Exception detection changed a bit. lampret 8820d 11h /or1k/tags/rel_24
50 Added CURINSN macro. lampret 8820d 11h /or1k/tags/rel_24
49 Changed simulation mode to non-virtual (real). lampret 8820d 11h /or1k/tags/rel_24
48 Added CCR. lampret 8820d 11h /or1k/tags/rel_24
47 Added interrupt recognition and better memory dump. lampret 8820d 11h /or1k/tags/rel_24

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.