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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl] - Rev 569

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Rev Log message Author Age Path
569 Default ASIC configuration does not sample WB inputs. lampret 8246d 16h /or1k/tags/rel_25/or1200/rtl
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8246d 19h /or1k/tags/rel_25/or1200/rtl
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8253d 01h /or1k/tags/rel_25/or1200/rtl
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8257d 04h /or1k/tags/rel_25/or1200/rtl
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8257d 17h /or1k/tags/rel_25/or1200/rtl
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8287d 21h /or1k/tags/rel_25/or1200/rtl
401 *** empty log message *** simons 8291d 07h /or1k/tags/rel_25/or1200/rtl
400 force_dslot_fetch does not work - allways zero. simons 8291d 07h /or1k/tags/rel_25/or1200/rtl
399 Trap insn couses break after exits ex_insn. simons 8291d 07h /or1k/tags/rel_25/or1200/rtl
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8294d 03h /or1k/tags/rel_25/or1200/rtl
390 Changed instantiation name of VS RAMs. lampret 8294d 04h /or1k/tags/rel_25/or1200/rtl
387 Now FPGA and ASIC target are separate. lampret 8294d 06h /or1k/tags/rel_25/or1200/rtl
386 Fixed VS RAM instantiation - again. lampret 8294d 06h /or1k/tags/rel_25/or1200/rtl
370 Program counter divided to PPC and NPC. simons 8298d 04h /or1k/tags/rel_25/or1200/rtl
367 Changed DSR/DRR behavior and exception detection. lampret 8298d 17h /or1k/tags/rel_25/or1200/rtl
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8299d 12h /or1k/tags/rel_25/or1200/rtl
360 Added OR1200_REGISTERED_INPUTS. lampret 8301d 04h /or1k/tags/rel_25/or1200/rtl
359 Added optional sampling of inputs. lampret 8301d 04h /or1k/tags/rel_25/or1200/rtl
358 Fixed virtual silicon single-port rams instantiation. lampret 8301d 04h /or1k/tags/rel_25/or1200/rtl
357 Fixed dbg_is_o assignment width. lampret 8301d 04h /or1k/tags/rel_25/or1200/rtl
356 Break point bug fixed simons 8301d 07h /or1k/tags/rel_25/or1200/rtl
354 Fixed width of du_except. lampret 8302d 01h /or1k/tags/rel_25/or1200/rtl
353 Cashes disabled. simons 8302d 11h /or1k/tags/rel_25/or1200/rtl
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8303d 14h /or1k/tags/rel_25/or1200/rtl
351 Fixed some l.trap typos. lampret 8303d 16h /or1k/tags/rel_25/or1200/rtl
350 For GDB changed single stepping and disabled trap exception. lampret 8303d 17h /or1k/tags/rel_25/or1200/rtl
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8308d 16h /or1k/tags/rel_25/or1200/rtl
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8308d 16h /or1k/tags/rel_25/or1200/rtl
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8310d 00h /or1k/tags/rel_25/or1200/rtl
316 Fixed exceptions. lampret 8311d 22h /or1k/tags/rel_25/or1200/rtl

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