OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_25] - Rev 1116

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1116 There was a bug in the simulator's UART implementation that caused the
UART's LSR register to become corrupted. This was due to an
assumption that 'char' is an unsigned type, but that is not true on
all platforms.

When the char type is signed and a character is read in the range
0x80-0xff, the high bit is sign-extended into the upper bits of an
entry in the receive FIFO. When the character reaches the head of the
FIFO, the upper bits of the FIFO entry are OR'ed into the LSR, causing
the LSR to be set to 0xFF.

A simple cast fixes the problem.		 sfurman 7838d 15h /or1k/tags/rel_25
1115 Fix stack-walking code in or1k_frame_chain() and or1k_skip_prologue()
to expect the function prologue that or32 gcc currently emits, rather
than a previous incarnation of the or1k ABI.		 sfurman 7854d 14h /or1k/tags/rel_25
1114 Added cvs log keywords lampret 7869d 09h /or1k/tags/rel_25
1113 Typos by Maria Bolado lampret 7869d 10h /or1k/tags/rel_25
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7875d 10h /or1k/tags/rel_25
1111 Small fix for path of tth binary. lampret 7884d 16h /or1k/tags/rel_25
1110 Re-generated. lampret 7884d 17h /or1k/tags/rel_25
1109 Temp files should rather not be in the cvs repository. lampret 7884d 17h /or1k/tags/rel_25
1108 Errors fixed. lampret 7884d 17h /or1k/tags/rel_25
1107 Updatded and improved formatting. lampret 7884d 17h /or1k/tags/rel_25
1106 Cache invalidate bug fixed again (it was ok before). simons 7918d 21h /or1k/tags/rel_25
1105 Added WB b3 signals lampret 7920d 04h /or1k/tags/rel_25
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7920d 04h /or1k/tags/rel_25
1103 sync problem in cuc not yet fixed markom 7924d 23h /or1k/tags/rel_25
1102 few cuc bug fixes markom 7924d 23h /or1k/tags/rel_25
1101 cuc now compiles markom 7925d 02h /or1k/tags/rel_25
1100 cvs problem fixed markom 7925d 02h /or1k/tags/rel_25
1099 cvs bug fixed markom 7925d 02h /or1k/tags/rel_25
1098 small bug in cuc fixed markom 7925d 02h /or1k/tags/rel_25
1097 Cache invalidate bug fixed. simons 7925d 16h /or1k/tags/rel_25
1096 An example of SW and RTL regression log because many people asked for. lampret 7931d 13h /or1k/tags/rel_25
1095 eval_reg replaced with the new evalsim_reg32 lampret 7932d 10h /or1k/tags/rel_25
1094 sys/time.h might not be available for or1k target lampret 7932d 11h /or1k/tags/rel_25
1093 New UART rx/tx fiel settings (due to or1ksim upgrade) lampret 7932d 11h /or1k/tags/rel_25
1092 Changed from or32-rtems toolchain to or32-uclinux. lampret 7932d 11h /or1k/tags/rel_25
1091 Added mmu test. lampret 7932d 11h /or1k/tags/rel_25
1090 Removed ic_invalidate lampret 7932d 11h /or1k/tags/rel_25
1089 Added dhrystone 2.1 benchmark lampret 7932d 11h /or1k/tags/rel_25
1088 Changed from or32-rtems toolchain to or32-uclinux. lampret 7932d 12h /or1k/tags/rel_25
1087 Changed or32-rtems to or32-uclinux. lampret 7932d 12h /or1k/tags/rel_25

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.