OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5588d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1253 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7443d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1252 preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. lampret 7443d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1226 interface to debug changed; no more opselect; stb-ack protocol markom 7470d 07h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1225 Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added andreje 7473d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1220 Exception prefix configuration changed. simons 7499d 00h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1207 Static exception prefix. lampret 7511d 13h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1171 Added embedded memory QMEM. lampret 7660d 22h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7693d 10h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7736d 13h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1155 No functional change. Only added customization for exception vectors. lampret 7739d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7752d 16h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7753d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7873d 04h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1078 Previous check-in was done by mistake. mohor 7913d 22h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1077 Signal scanb_sen renamed to scanb_en. mohor 7913d 22h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7924d 17h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1055 Removed obsolete comment. lampret 7956d 10h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7964d 07h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7964d 18h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7965d 08h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7968d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7968d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7981d 11h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
984 Disable SB until it is tested lampret 7984d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
977 Added store buffer. lampret 7984d 17h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7988d 07h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 7991d 08h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8019d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v
870 Added defines for enabling generic FF based memory macro for register file. lampret 8055d 21h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.