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[/] [or1k/] [tags/] [rel_5/] [or1200/] - Rev 916

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Rev Log message Author Age Path
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8010d 02h /or1k/tags/rel_5/or1200
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8026d 05h /or1k/tags/rel_5/or1200
871 Generic flip-flop based memory macro for register file. lampret 8062d 11h /or1k/tags/rel_5/or1200
870 Added defines for enabling generic FF based memory macro for register file. lampret 8062d 11h /or1k/tags/rel_5/or1200
869 Added generic flip-flop based memory macro instantiation. lampret 8062d 11h /or1k/tags/rel_5/or1200
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8133d 11h /or1k/tags/rel_5/or1200
794 Added again just recently removed full_case directive lampret 8133d 11h /or1k/tags/rel_5/or1200
791 Fixed some ports in instnatiations that were removed from the modules lampret 8133d 11h /or1k/tags/rel_5/or1200
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8133d 11h /or1k/tags/rel_5/or1200
788 Some of the warnings fixed. lampret 8133d 12h /or1k/tags/rel_5/or1200
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8134d 08h /or1k/tags/rel_5/or1200
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8134d 09h /or1k/tags/rel_5/or1200
776 Updated defines. lampret 8134d 09h /or1k/tags/rel_5/or1200
775 Optimized cache controller FSM. lampret 8134d 09h /or1k/tags/rel_5/or1200
774 Removed old files. lampret 8134d 09h /or1k/tags/rel_5/or1200
737 Added alternative for critical path in DU. lampret 8149d 03h /or1k/tags/rel_5/or1200
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8152d 02h /or1k/tags/rel_5/or1200
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8152d 02h /or1k/tags/rel_5/or1200
668 Lapsus fixed. simons 8176d 12h /or1k/tags/rel_5/or1200
663 No longer using async rst as sync reset for the counter. lampret 8179d 02h /or1k/tags/rel_5/or1200
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8179d 23h /or1k/tags/rel_5/or1200
636 Fixed combinational loops. lampret 8189d 08h /or1k/tags/rel_5/or1200
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8194d 02h /or1k/tags/rel_5/or1200
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8198d 20h /or1k/tags/rel_5/or1200
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8202d 14h /or1k/tags/rel_5/or1200
596 SR[TEE] should be zero after reset. lampret 8202d 18h /or1k/tags/rel_5/or1200
595 Fixed 'the NPC single-step fix'. lampret 8203d 13h /or1k/tags/rel_5/or1200
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8203d 20h /or1k/tags/rel_5/or1200
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8206d 22h /or1k/tags/rel_5/or1200
571 Changed alignment exception EPCR. Not tested yet. lampret 8207d 07h /or1k/tags/rel_5/or1200

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