OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_8/] [or1200/] - Rev 1778

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5623d 08h /or1k/tags/rel_8/or1200
1084 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7939d 17h /or1k/tags/rel_8/or1200
1083 SB mem width fixed. simons 7939d 17h /or1k/tags/rel_8/or1200
1079 RAMs wrong connected to the BIST scan chain. mohor 7948d 15h /or1k/tags/rel_8/or1200
1078 Previous check-in was done by mistake. mohor 7948d 16h /or1k/tags/rel_8/or1200
1077 Signal scanb_sen renamed to scanb_en. mohor 7948d 16h /or1k/tags/rel_8/or1200
1069 Signal scanb_eni renamed to scanb_en mohor 7952d 09h /or1k/tags/rel_8/or1200
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7959d 11h /or1k/tags/rel_8/or1200
1055 Removed obsolete comment. lampret 7991d 04h /or1k/tags/rel_8/or1200
1054 Fixed a combinational loop. lampret 7991d 04h /or1k/tags/rel_8/or1200
1053 Disabled cache inhibit atttribute. lampret 7991d 04h /or1k/tags/rel_8/or1200
1040 Updated the script. lampret 7998d 10h /or1k/tags/rel_8/or1200
1039 Added linter directory. lampret 7998d 10h /or1k/tags/rel_8/or1200
1038 Fixed a typo, reported by Taylor Su. lampret 7998d 12h /or1k/tags/rel_8/or1200
1037 First import of the new synopsys DC scripts. lampret 7998d 12h /or1k/tags/rel_8/or1200
1036 Removed old synthesis scripts. lampret 7998d 13h /or1k/tags/rel_8/or1200
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7999d 01h /or1k/tags/rel_8/or1200
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7999d 12h /or1k/tags/rel_8/or1200
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8000d 02h /or1k/tags/rel_8/or1200
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8003d 06h /or1k/tags/rel_8/or1200
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8003d 09h /or1k/tags/rel_8/or1200
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8010d 06h /or1k/tags/rel_8/or1200
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8016d 05h /or1k/tags/rel_8/or1200
993 Fixed IMMU bug. lampret 8016d 05h /or1k/tags/rel_8/or1200
984 Disable SB until it is tested lampret 8019d 09h /or1k/tags/rel_8/or1200
977 Added store buffer. lampret 8019d 11h /or1k/tags/rel_8/or1200
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8023d 01h /or1k/tags/rel_8/or1200
960 Directory cleanup. lampret 8023d 02h /or1k/tags/rel_8/or1200
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8024d 01h /or1k/tags/rel_8/or1200
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8026d 02h /or1k/tags/rel_8/or1200

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.