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[/] [or1k/] [tags/] [rel_9] - Rev 642

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642 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8196d 22h /or1k/tags/rel_9
641 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8196d 23h /or1k/tags/rel_9
640 Merge profiler and mprofiler with sim. ivang 8197d 00h /or1k/tags/rel_9
639 MMU cache inhibit bit test added. simons 8199d 14h /or1k/tags/rel_9
638 TLBTR CI bit is now working properly. simons 8199d 15h /or1k/tags/rel_9
637 Updated file names. lampret 8199d 16h /or1k/tags/rel_9
636 Fixed combinational loops. lampret 8199d 16h /or1k/tags/rel_9
635 Fixed Makefile bug. ivang 8199d 18h /or1k/tags/rel_9
634 configure.in : fixed to build start/Makefile
start.S : l.jalr r9 -> l.jr r9

Added missing files.		 ivang 8200d 19h /or1k/tags/rel_9
633 Bug fix in command line parser. ivang 8200d 20h /or1k/tags/rel_9
632 profiler and mprofiler merged into sim. ivang 8201d 15h /or1k/tags/rel_9
631 Real cache access is simulated now. simons 8202d 14h /or1k/tags/rel_9
630 some bug fixes in store buffer analysis markom 8202d 23h /or1k/tags/rel_9
629 typo fixed markom 8203d 02h /or1k/tags/rel_9
627 or32 restored markom 8203d 03h /or1k/tags/rel_9
626 store buffer added markom 8203d 03h /or1k/tags/rel_9
625 Bus error bug fixed. Cache routines added. simons 8203d 19h /or1k/tags/rel_9
624 Added logging of writes/read to/from SPR registers. ivang 8203d 19h /or1k/tags/rel_9
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8203d 21h /or1k/tags/rel_9
622 Cache test works on hardware. simons 8204d 00h /or1k/tags/rel_9
621 Cache test works on hardware. simons 8204d 01h /or1k/tags/rel_9
620 use ARITH_SET_FLAG to turn off set flag by arith. instructions markom 8204d 02h /or1k/tags/rel_9
619 all test pass, after newest changes markom 8204d 02h /or1k/tags/rel_9
618 Fixed display of new 'void' nop insns. lampret 8204d 10h /or1k/tags/rel_9
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8204d 11h /or1k/tags/rel_9
616 flags test added markom 8206d 21h /or1k/tags/rel_9
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8206d 21h /or1k/tags/rel_9
614 Changed to support new debug if. simons 8207d 04h /or1k/tags/rel_9
613 init: trap exception occurs always; initialization of sr not needed anymore markom 8208d 01h /or1k/tags/rel_9
612 Tick timer period extended to meet real timing. simons 8208d 02h /or1k/tags/rel_9

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