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[/] [or1k/] [tags/] [stable_0_1_0/] [or1ksim/] [mmu/] [dmmu.c] - Rev 1780

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1765 root 5601d 10h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
1357 This commit was manufactured by cvs2svn to create tag 'stable_0_1_0'. 7089d 23h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7089d 23h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7091d 15h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7104d 19h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7296d 10h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
1240 additional functions to bypass cache and mmu needed for peripheral devices phoenix 7468d 05h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7993d 00h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
886 MMU registers reserved fields protected from writing. simons 8036d 17h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8036d 23h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
638 TLBTR CI bit is now working properly. simons 8195d 12h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8208d 10h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
572 Some new bugs fixed. simons 8213d 12h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8219d 20h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
535 stats is updated; statical single stats removed; t command output cleaned, added time output; cycles is moved to instructions; cycles now count time markom 8220d 19h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
456 Page size bug fixed. simons 8244d 14h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
438 ITLB -> DTLB lapsus fixed. simons 8246d 19h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
430 dpfault and ipfault exceptions implemented markom 8247d 18h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
429 cache configuration added markom 8247d 19h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
425 immu and dmmu configurations added markom 8247d 20h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8274d 22h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8372d 19h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8455d 04h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8662d 01h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
62 OR1K DMMU model. lampret 8674d 02h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8896d 12h /or1k/tags/stable_0_1_0/or1ksim/mmu/dmmu.c

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