OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0] - Rev 86

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
86 Added dh command. lampret 8504d 21h /or1k/tags/stable_0_1_0
85 Added dumphex. lampret 8504d 21h /or1k/tags/stable_0_1_0
84 Update. lampret 8504d 21h /or1k/tags/stable_0_1_0
83 Updates. lampret 8504d 21h /or1k/tags/stable_0_1_0
82 Changed pctemp to pcnext. lampret 8504d 21h /or1k/tags/stable_0_1_0
80 First import. lampret 8532d 16h /or1k/tags/stable_0_1_0
79 Data and instruction cache simulation added. lampret 8534d 13h /or1k/tags/stable_0_1_0
78 (i/d)tlb_status lampret 8658d 03h /or1k/tags/stable_0_1_0
77 Regular update. lampret 8658d 03h /or1k/tags/stable_0_1_0
76 regular update lampret 8658d 03h /or1k/tags/stable_0_1_0
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8658d 03h /or1k/tags/stable_0_1_0
74 Same as DMMU. lampret 8665d 02h /or1k/tags/stable_0_1_0
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8665d 02h /or1k/tags/stable_0_1_0
72 Added 'how to build GNU tools' lampret 8670d 03h /or1k/tags/stable_0_1_0
71 Clean two typos. lampret 8675d 05h /or1k/tags/stable_0_1_0
70 Basic setjmp/longjmp are ready. lampret 8675d 05h /or1k/tags/stable_0_1_0
69 Sim debug. lampret 8677d 03h /or1k/tags/stable_0_1_0
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8677d 03h /or1k/tags/stable_0_1_0
67 Added simulator "application load". lampret 8677d 03h /or1k/tags/stable_0_1_0
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.
lampret 8677d 03h /or1k/tags/stable_0_1_0
65 Added DMMU stats. lampret 8677d 03h /or1k/tags/stable_0_1_0
64 SPR bit definition moved to spr_defs.h. lampret 8677d 03h /or1k/tags/stable_0_1_0
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).
lampret 8677d 03h /or1k/tags/stable_0_1_0
62 OR1K DMMU model. lampret 8677d 03h /or1k/tags/stable_0_1_0
61 2000-09-26 Joel Sherrill <joel@OARcorp.com>

* libc/sys/rtems/include/pthread.h: Added file missed by earlier
commit of RTEMS modifications.
joel 8691d 21h /or1k/tags/stable_0_1_0
60 Memory model changed. lampret 8712d 06h /or1k/tags/stable_0_1_0
59 2000-09-05 Joel Sherrill <joel@OARcorp.com>

* Merged newlib-1.8.2-rtems-20000905.diff which includes
or16 and or32 configuration support.
joel 8712d 17h /or1k/tags/stable_0_1_0
57 This commit was generated by cvs2svn to compensate for changes in r56, which
included commits to RCS files with non-trunk default branches.
joel 8718d 15h /or1k/tags/stable_0_1_0
55 Added 'dv' command for dumping memory as verilog model. lampret 8728d 03h /or1k/tags/stable_0_1_0
54 Regular maintenance. lampret 8728d 03h /or1k/tags/stable_0_1_0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.