OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_1_0] - Rev 98

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
98 Return value register is now r9. lampret 8501d 21h /or1k/tags/stable_0_1_0
97 Description of all test cases (at least working one). lampret 8501d 21h /or1k/tags/stable_0_1_0
96 First import. lampret 8503d 14h /or1k/tags/stable_0_1_0
95 Update. lampret 8511d 23h /or1k/tags/stable_0_1_0
94 Update. lampret 8532d 00h /or1k/tags/stable_0_1_0
93 Adding uos. lampret 8532d 00h /or1k/tags/stable_0_1_0
92 Tick timer. lampret 8532d 03h /or1k/tags/stable_0_1_0
91 Tick timer facility. lampret 8532d 03h /or1k/tags/stable_0_1_0
90 Added tick timer. lampret 8532d 04h /or1k/tags/stable_0_1_0
89 Minor changes. lampret 8533d 00h /or1k/tags/stable_0_1_0
88 Update. lampret 8533d 11h /or1k/tags/stable_0_1_0
87 Files required for creation of html files. lampret 8533d 12h /or1k/tags/stable_0_1_0
86 Added dh command. lampret 8533d 12h /or1k/tags/stable_0_1_0
85 Added dumphex. lampret 8533d 12h /or1k/tags/stable_0_1_0
84 Update. lampret 8533d 12h /or1k/tags/stable_0_1_0
83 Updates. lampret 8533d 12h /or1k/tags/stable_0_1_0
82 Changed pctemp to pcnext. lampret 8533d 12h /or1k/tags/stable_0_1_0
80 First import. lampret 8561d 06h /or1k/tags/stable_0_1_0
79 Data and instruction cache simulation added. lampret 8563d 04h /or1k/tags/stable_0_1_0
78 (i/d)tlb_status lampret 8686d 17h /or1k/tags/stable_0_1_0
77 Regular update. lampret 8686d 17h /or1k/tags/stable_0_1_0
76 regular update lampret 8686d 18h /or1k/tags/stable_0_1_0
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8686d 18h /or1k/tags/stable_0_1_0
74 Same as DMMU. lampret 8693d 17h /or1k/tags/stable_0_1_0
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8693d 17h /or1k/tags/stable_0_1_0
72 Added 'how to build GNU tools' lampret 8698d 18h /or1k/tags/stable_0_1_0
71 Clean two typos. lampret 8703d 19h /or1k/tags/stable_0_1_0
70 Basic setjmp/longjmp are ready. lampret 8703d 20h /or1k/tags/stable_0_1_0
69 Sim debug. lampret 8705d 17h /or1k/tags/stable_0_1_0
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8705d 17h /or1k/tags/stable_0_1_0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.