Rev |
Log message |
Author |
Age |
Path |
1765 |
|
root |
5589d 17h |
/or1k/tags/stable_0_2_0_rc1/insight |
1572 |
This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc1'. |
|
6864d 00h |
/or1k/tags/stable_0_2_0_rc1/insight |
1557 |
Fix most warnings issued by gcc4 |
nogj |
6872d 07h |
/or1k/tags/stable_0_2_0_rc1/insight |
1554 |
fixed l.maci encoding |
phoenix |
6889d 18h |
/or1k/tags/stable_0_2_0_rc1/insight |
1552 |
Update most config.guess and config.sub scripts. |
robertmh |
6917d 20h |
/or1k/tags/stable_0_2_0_rc1/insight |
1475 |
l.rfe does not have a delay slot. Don't mark it as such. |
nogj |
7002d 21h |
/or1k/tags/stable_0_2_0_rc1/insight |
1452 |
Implement a dynamic recompiler to speed up the execution |
nogj |
7030d 00h |
/or1k/tags/stable_0_2_0_rc1/insight |
1444 |
Move the definitions needed for the simple execution model out of or32.h and into simpl32_defs.h |
nogj |
7030d 00h |
/or1k/tags/stable_0_2_0_rc1/insight |
1440 |
Reclasify l.trap and l.sys to be an exception instruction |
nogj |
7030d 00h |
/or1k/tags/stable_0_2_0_rc1/insight |
1384 |
Fix the parameters to the l.ff1/l.maci instructions |
nogj |
7045d 04h |
/or1k/tags/stable_0_2_0_rc1/insight |
1350 |
Mark a simulated cpu address as such, by introducing the new oraddr_t type |
nogj |
7079d 22h |
/or1k/tags/stable_0_2_0_rc1/insight |
1346 |
Remove the global op structure |
nogj |
7093d 02h |
/or1k/tags/stable_0_2_0_rc1/insight |
1344 |
* Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes |
nogj |
7093d 02h |
/or1k/tags/stable_0_2_0_rc1/insight |
1342 |
* Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option. |
nogj |
7093d 02h |
/or1k/tags/stable_0_2_0_rc1/insight |
1341 |
Mark wich operand is the destination operand in the architechture definition |
nogj |
7093d 03h |
/or1k/tags/stable_0_2_0_rc1/insight |
1338 |
l.ff1 instruction added |
andreje |
7109d 00h |
/or1k/tags/stable_0_2_0_rc1/insight |
1333 |
gcc 3.4 compile fix |
phoenix |
7124d 01h |
/or1k/tags/stable_0_2_0_rc1/insight |
1309 |
removed includes |
phoenix |
7281d 20h |
/or1k/tags/stable_0_2_0_rc1/insight |
1308 |
Gyorgy Jeney: extensive cleanup |
phoenix |
7284d 17h |
/or1k/tags/stable_0_2_0_rc1/insight |
1295 |
Updated instruction set descriptions. Changed FP instructions encoding. |
lampret |
7306d 17h |
/or1k/tags/stable_0_2_0_rc1/insight |
1286 |
Changed desciption of the l.cust5 insns |
lampret |
7355d 20h |
/or1k/tags/stable_0_2_0_rc1/insight |
1285 |
Changed desciption of the l.cust5 insns |
lampret |
7355d 20h |
/or1k/tags/stable_0_2_0_rc1/insight |
1256 |
page size is 8192 on or32 |
phoenix |
7440d 20h |
/or1k/tags/stable_0_2_0_rc1/insight |
1169 |
Added support for l.addc instruction. |
csanchez |
7668d 20h |
/or1k/tags/stable_0_2_0_rc1/insight |
1152 |
*** empty log message *** |
phoenix |
7748d 23h |
/or1k/tags/stable_0_2_0_rc1/insight |
1149 |
*** empty log message *** |
phoenix |
7749d 13h |
/or1k/tags/stable_0_2_0_rc1/insight |
1144 |
Speed up gdb when running with serial targets:
When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)
When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump. |
sfurman |
7751d 19h |
/or1k/tags/stable_0_2_0_rc1/insight |
1142 |
Speed up gdb when running with serial targets:
When generating backtraces, the prologue of each function is scanned
at least three times by architecture-independent code, e.g. to
determine offsets of saved registers, identify frameless functions,
etc. This new code adds straightforward caching of the information
gleaned by or1k_scan_prologue() on a per-frame basis rather than
storing it in global static variables. (This benefits both JTAG and
serial gdb targets, though the JTAG target runs fast enough that it is
not particularly needed.)
When the register set is dumped by the serial target, e.g. at any
breakpoint or interrupt, the 32 vector/FP registers were included in
the dump (each 8 bytes long), though they aren't implemented. The new
code tells gdb that unimplemented registers have zero length in the
dump. |
sfurman |
7752d 10h |
/or1k/tags/stable_0_2_0_rc1/insight |
1124 |
Initialize or1k_implementation with reasonable defaults for the number
of implementation registers. This doesn't affect the jtag or sim
targets at all because those values are always overwritten when
or1k_implementation is initialized. However, it is necessary when
connecting to remote gdb stubs through a serial port or socket, since
or1k_implementation is not yet initialized for those targets. |
sfurman |
7785d 12h |
/or1k/tags/stable_0_2_0_rc1/insight |
1123 |
Renumber/rename SPRs to match latest architecture doc |
sfurman |
7786d 19h |
/or1k/tags/stable_0_2_0_rc1/insight |