OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [mmu/] - Rev 997

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
997 PRINTF should be used instead of printf; command redirection repaired markom 7998d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
970 Testbench is now running on ORP architecture platform. simons 8005d 17h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
886 MMU registers reserved fields protected from writing. simons 8041d 23h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
884 code cleaning - a lot of global variables moved to runtime struct markom 8042d 04h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
876 Beta release of ATA simulation rherveille 8049d 16h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
713 lot of small minor improvements: code documented, cleaned; runs at about same speed when not actually logging, but exe_log is enabled; raw_stats now run only with simple execution - enable RAW_USAGE_STATS macro markom 8170d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
638 TLBTR CI bit is now working properly. simons 8200d 18h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8213d 16h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
572 Some new bugs fixed. simons 8218d 18h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8225d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
535 stats is updated; statical single stats removed; t command output cleaned, added time output; cycles is moved to instructions; cycles now count time markom 8226d 00h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
517 some performance optimizations markom 8229d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
500 Added .cvsignore files for annoying generated files erez 8231d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
456 Page size bug fixed. simons 8249d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
446 ITLBMR register bit fields set in order. simons 8251d 07h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
438 ITLB -> DTLB lapsus fixed. simons 8252d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
430 dpfault and ipfault exceptions implemented markom 8253d 00h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
429 cache configuration added markom 8253d 00h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
425 immu and dmmu configurations added markom 8253d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
416 IMMU bugs fixed. simons 8255d 15h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8280d 03h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8301d 04h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
204 Added function prototypes to stop gcc from complaining erez 8335d 02h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8378d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8460d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
74 Same as DMMU. lampret 8667d 07h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8667d 07h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
62 OR1K DMMU model. lampret 8679d 07h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
18 or16 added, or1k renamed to or32. lampret 8840d 07h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu
13 Rebuild of the generated files. jrydberg 8900d 23h /or1k/tags/stable_0_2_0_rc1/or1ksim/mmu

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.