OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [sim-config.h] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5566d 18h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1572 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc1'. 6841d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1557 Fix most warnings issued by gcc4 nogj 6849d 08h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1550 * prototype() -> prototype(void) where appropriate.
* Use `static' where it can be used.		 nogj 6910d 21h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1539 Speed up the dmmu nogj 6911d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1538 Speed up the immu nogj 6911d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1537 Remove old spr logging code. Use `-d +spr' to get spr access logged to stderr nogj 6911d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.		 nogj 6959d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1485 Remove nolonger used test peripheral nogj 6959d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1471 Rewrite the interactive mode handling to also work in the recompiler nogj 7007d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1455 Remove nolonger needed --output-cfg option nogj 7007d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1446 Cosmetic fixes nogj 7007d 01h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1375 Remove FAST_SIM, it nolonger provides a speed up nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1374 Cleanup the gpio peripheral useing the new callbacks nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1373 Cleanup the memory controller useing the new callbacks nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1372 Cleanup ethernet peripheral, useing the new callbacks nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1371 Cleanup kbd peripheral useing the new callbacks nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1370 Cleanup dma peripheral useing the new callbacks nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1369 Cleanup FB peripheral, useing the new callbacks nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1368 Cleanup VGA peripheral useing the new callbacks nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1367 Cleanup uart peripheral useing the new callback mechanism nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1364 Clean up the ata peripheral useing the new set of callbacks nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1363 Add status callback nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1361 Cleanup test peripheral nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1360 Add dynamic hooks to sim_reset nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7047d 20h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1353 Modularise simulator command parsing nogj 7056d 23h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1320 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7173d 18h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1308 Gyorgy Jeney: extensive cleanup phoenix 7261d 18h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h
1076 channels integration rprescott 7892d 19h /or1k/tags/stable_0_2_0_rc1/or1ksim/sim-config.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.