OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [toplevel.c] - Rev 1780

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5583d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1611 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc2'. 6783d 13h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1609 0.2.0-rc2 release nogj 6783d 13h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1607 Don't drop cycles from the scheduler nogj 6784d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1593 Don't kill sim on second ctrl+c if the cli prompt has already been shown nogj 6803d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1557 Fix most warnings issued by gcc4 nogj 6865d 17h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1550 * prototype() -> prototype(void) where appropriate.
* Use `static' where it can be used.
nogj 6927d 06h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1548 Print the useage of the -d in the help text nogj 6927d 06h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1539 Speed up the dmmu nogj 6927d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1538 Speed up the immu nogj 6927d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1537 Remove old spr logging code. Use `-d +spr' to get spr access logged to stderr nogj 6927d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1506 * Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions.
nogj 6932d 14h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.
nogj 6975d 15h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1480 Kill the sim on the second ctrl-c nogj 6996d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1471 Rewrite the interactive mode handling to also work in the recompiler nogj 7023d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1455 Remove nolonger needed --output-cfg option nogj 7023d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1452 Implement a dynamic recompiler to speed up the execution nogj 7023d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1446 Cosmetic fixes nogj 7023d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7023d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7023d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1402 Do what dc_clock() did in mtspr() and remove it nogj 7023d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1390 * Change scheduler to count down to 0 instead of reaching a certain cycle
count.
* Change the SCHED_ADD interface to take a time out as the parameter instead of the number of cycles.
nogj 7023d 10h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1387 Remove pic_clock() nogj 7029d 14h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1375 Remove FAST_SIM, it nolonger provides a speed up nogj 7064d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1374 Cleanup the gpio peripheral useing the new callbacks nogj 7064d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1373 Cleanup the memory controller useing the new callbacks nogj 7064d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1372 Cleanup ethernet peripheral, useing the new callbacks nogj 7064d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1371 Cleanup kbd peripheral useing the new callbacks nogj 7064d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1370 Cleanup dma peripheral useing the new callbacks nogj 7064d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c
1369 Cleanup FB peripheral, useing the new callbacks nogj 7064d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/toplevel.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.