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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [gen_or1k_isa/] [sources/] [opcode/] [or32.c] - Rev 1780

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1765 root 5606d 19h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1648 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc3'. 6753d 22h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6753d 22h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1605 Execute l.ff1 instruction nogj 6814d 23h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1597 Fix parsing the destination register nogj 6827d 01h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1590 Added l.fl1 lampret 6829d 22h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1557 Fix most warnings issued by gcc4 nogj 6889d 09h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1554 fixed l.maci encoding phoenix 6906d 19h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1475 l.rfe does not have a delay slot. Don't mark it as such. nogj 7019d 22h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1452 Implement a dynamic recompiler to speed up the execution nogj 7047d 01h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1440 Reclasify l.trap and l.sys to be an exception instruction nogj 7047d 01h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1384 Fix the parameters to the l.ff1/l.maci instructions nogj 7062d 05h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7097d 00h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1346 Remove the global op structure nogj 7110d 03h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.		 nogj 7110d 04h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1341 Mark wich operand is the destination operand in the architechture definition nogj 7110d 04h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1338 l.ff1 instruction added andreje 7126d 02h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1309 removed includes phoenix 7298d 21h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7301d 18h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1295 Updated instruction set descriptions. Changed FP instructions encoding. lampret 7323d 18h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1286 Changed desciption of the l.cust5 insns lampret 7372d 22h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1285 Changed desciption of the l.cust5 insns lampret 7372d 22h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1169 Added support for l.addc instruction. csanchez 7685d 22h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1114 Added cvs log keywords lampret 7840d 14h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
1034 Fixed encoding for l.div/l.divu. lampret 7982d 15h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
879 Initial version of OpenRISC Custom Unit Compiler added markom 8048d 01h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
801 l.muli instruction added markom 8140d 04h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
722 floating point registers are obsolete; GPRs should be used instead markom 8168d 04h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
720 single floating point support added markom 8168d 08h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c
717 some minor improvements markom 8168d 10h /or1k/tags/stable_0_2_0_rc3/gen_or1k_isa/sources/opcode/or32.c

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