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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [cpu/] - Rev 49

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Rev Log message Author Age Path
49 Changed simulation mode to non-virtual (real). lampret 8788d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
48 Added CCR. lampret 8788d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
47 Added interrupt recognition and better memory dump. lampret 8788d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
43 SUPV bit from SR is now saved into EPCR bit 0. lampret 8798d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
42 Bug fix. Only symbols with names shorter than 9 characters are loaded. lampret 8798d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
41 Bug fix. Now all COFF sections are loaded not just .text. lampret 8799d 14h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
38 Virtual machine at the moment. lampret 8799d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
37 STACK_SIZE is not properly used (will be removed soon). lampret 8799d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
36 Fixed bug when loading "data" from .text segment (all insns are not only
decoded but also placed in simulator memory undecoded as data).		 lampret 8799d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
35 SLP hooks. lampret 8799d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
34 Started with SLP (not finished yet). lampret 8799d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
33 Handling of or1k exceptions. lampret 8803d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
32 Interrupt recognition. lampret 8803d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
30 Updated SPRs, exceptions. Added 16450 device. lampret 8803d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
29 Adding OR16/OR32 insn decoder. lampret 8818d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
28 Adding COFF loader. lampret 8818d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
26 Clean up. lampret 8834d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
25 Bug fix in handling labels when loading code into simulator memory. lampret 8834d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
24 Static branch prediction added. lampret 8834d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
23 Common OR1K backend for OR32 and OR16. lampret 8834d 16h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
22 More modifications related to or16. lampret 8836d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
20 or1k renamed to or32. lampret 8837d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
19 Added or16, or1k renamed to or32. lampret 8837d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
18 or16 added, or1k renamed to or32. lampret 8837d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
13 Rebuild of the generated files. jrydberg 8898d 03h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
8 Initial revision. jrydberg 8898d 03h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.		 jrydberg 8898d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8898d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 cvs 9024d 15h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu

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