OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [sim.cfg] - Rev 1367

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1367 Cleanup uart peripheral useing the new callback mechanism nogj 7084d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
1364 Clean up the ata peripheral useing the new set of callbacks nogj 7084d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
1126 Added lengthy comment explaining all possible choices for UART
channels, e.g. xterm, tcp, file, etc.		 sfurman 7778d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
1076 channels integration rprescott 7929d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
1021 *** empty log message *** rherveille 7987d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
897 improved CUC GUI; pre/unroll bugs fixed markom 8032d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
883 cuc updated, cuc prompt parsing; CSM analysis markom 8040d 01h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
879 Initial version of OpenRISC Custom Unit Compiler added markom 8045d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
876 Beta release of ATA simulation rherveille 8046d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
730 tick section is now obsolete; update your .cfg files! markom 8164d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
725 Added some more configuration parameters. ivang 8165d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
724 Configuration of ethernet model socket interface and IRQ added. ivang 8165d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
702 Initial coding of ethernet simulator model finished. ivang 8172d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
689 profiling disabled in sample configuration markom 8179d 10h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
675 register output added to sw executed log markom 8184d 05h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
672 advanced exe_log functionality added markom 8184d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
664 very simple PS/2 keyboard model with associated test added markom 8187d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
648 fb now works in system memory markom 8193d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
645 simple frame buffer peripheral with test added markom 8194d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
632 profiler and mprofiler merged into sim. ivang 8199d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
629 typo fixed markom 8201d 07h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
626 store buffer added markom 8201d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
624 Added logging of writes/read to/from SPR registers. ivang 8202d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
599 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8210d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
568 include command added to cfg script markom 8216d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
557 some optimizations; fsim running at 2MIPS; pm section added to config; configure bug fixed markom 8220d 07h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
556 support for SPR_SR_EP added; cpu.sr added to config markom 8220d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
553 FLASH and RAM were named incorrectly markom 8220d 10h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
549 enabled parameters removed from devices, which also have number of devices; command line --output-cfg parameter added markom 8221d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg
547 memory profiler added markom 8221d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/sim.cfg

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.