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[/] [or1k/] [tags/] [stable_0_2_0_rc3] - Rev 208

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Rev Log message Author Age Path
208 Initial checkin with working port to or1k chris 8355d 08h /or1k/tags/stable_0_2_0_rc3
207 Several major changes to allow gdb to work with an Or1k implementation
that does not need a writeable PC. This version will use the breakpoint
vector and install a new vector into the EPC register, and then single
step out of the breakpoint exception. The breakpoint exception vector
must include only 2 commands: l.rfe and l.nop. Anything else and this
gdb version will fail w/ or1ksim.		 chris 8355d 12h /or1k/tags/stable_0_2_0_rc3
206 Several modifications to support gdb in a new exception style mode.
This new version works with gdb, and does not require the simulator
to implement a writeable PC.		 chris 8355d 12h /or1k/tags/stable_0_2_0_rc3
205 Adding debug capabilities. Half done. lampret 8359d 15h /or1k/tags/stable_0_2_0_rc3
204 Added function prototypes to stop gcc from complaining erez 8362d 07h /or1k/tags/stable_0_2_0_rc3
203 Updated from xess branch. lampret 8363d 20h /or1k/tags/stable_0_2_0_rc3
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf		 erez 8369d 04h /or1k/tags/stable_0_2_0_rc3
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8369d 04h /or1k/tags/stable_0_2_0_rc3
200 Initial import simons 8372d 11h /or1k/tags/stable_0_2_0_rc3
199 Initial import simons 8372d 12h /or1k/tags/stable_0_2_0_rc3
198 Moved from testbench.old simons 8374d 23h /or1k/tags/stable_0_2_0_rc3
197 This is not used any more. simons 8374d 23h /or1k/tags/stable_0_2_0_rc3
196 Configuration SPRs added. simons 8375d 00h /or1k/tags/stable_0_2_0_rc3
195 New test added. simons 8375d 00h /or1k/tags/stable_0_2_0_rc3
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.		 chris 8375d 08h /or1k/tags/stable_0_2_0_rc3
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8375d 08h /or1k/tags/stable_0_2_0_rc3
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.		 chris 8375d 17h /or1k/tags/stable_0_2_0_rc3
191 Added UART jitter var to sim config chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
190 Added jitter initialization chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
189 fixed mode handling for tick facility chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
188 fixed PIC interrupt controller chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
187 minor change to clear pending exception chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
186 major change to UART structure chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
185 major change to UART code chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
184 modified decode for trace debugging chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
183 changed special case for PICSR chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
182 updated exception handling procedures chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
181 Added trace/stall commands chris 8376d 14h /or1k/tags/stable_0_2_0_rc3
180 Updated debug. lampret 8376d 19h /or1k/tags/stable_0_2_0_rc3
179 Sim run script lampret 8396d 12h /or1k/tags/stable_0_2_0_rc3

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