OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3] - Rev 653

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
653 Some cleanup. simons 8224d 06h /or1k/tags/stable_0_2_0_rc3
652 Some cleanup. simons 8224d 07h /or1k/tags/stable_0_2_0_rc3
651 Some cleanup. simons 8224d 07h /or1k/tags/stable_0_2_0_rc3
650 Some cleanup. simons 8224d 08h /or1k/tags/stable_0_2_0_rc3
649 Some cleanup. simons 8224d 08h /or1k/tags/stable_0_2_0_rc3
648 fb now works in system memory markom 8225d 17h /or1k/tags/stable_0_2_0_rc3
647 some changes to fb to make it compatible with HW markom 8226d 12h /or1k/tags/stable_0_2_0_rc3
646 some bugs fixed markom 8226d 13h /or1k/tags/stable_0_2_0_rc3
645 simple frame buffer peripheral with test added markom 8226d 17h /or1k/tags/stable_0_2_0_rc3
644 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8227d 12h /or1k/tags/stable_0_2_0_rc3
643 Quick bug fix. ivang 8227d 12h /or1k/tags/stable_0_2_0_rc3
642 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8227d 12h /or1k/tags/stable_0_2_0_rc3
641 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8227d 13h /or1k/tags/stable_0_2_0_rc3
640 Merge profiler and mprofiler with sim. ivang 8227d 14h /or1k/tags/stable_0_2_0_rc3
639 MMU cache inhibit bit test added. simons 8230d 05h /or1k/tags/stable_0_2_0_rc3
638 TLBTR CI bit is now working properly. simons 8230d 05h /or1k/tags/stable_0_2_0_rc3
637 Updated file names. lampret 8230d 06h /or1k/tags/stable_0_2_0_rc3
636 Fixed combinational loops. lampret 8230d 06h /or1k/tags/stable_0_2_0_rc3
635 Fixed Makefile bug. ivang 8230d 08h /or1k/tags/stable_0_2_0_rc3
634 configure.in : fixed to build start/Makefile
start.S : l.jalr r9 -> l.jr r9

Added missing files.
ivang 8231d 09h /or1k/tags/stable_0_2_0_rc3
633 Bug fix in command line parser. ivang 8231d 10h /or1k/tags/stable_0_2_0_rc3
632 profiler and mprofiler merged into sim. ivang 8232d 05h /or1k/tags/stable_0_2_0_rc3
631 Real cache access is simulated now. simons 8233d 04h /or1k/tags/stable_0_2_0_rc3
630 some bug fixes in store buffer analysis markom 8233d 13h /or1k/tags/stable_0_2_0_rc3
629 typo fixed markom 8233d 16h /or1k/tags/stable_0_2_0_rc3
627 or32 restored markom 8233d 17h /or1k/tags/stable_0_2_0_rc3
626 store buffer added markom 8233d 17h /or1k/tags/stable_0_2_0_rc3
625 Bus error bug fixed. Cache routines added. simons 8234d 09h /or1k/tags/stable_0_2_0_rc3
624 Added logging of writes/read to/from SPR registers. ivang 8234d 09h /or1k/tags/stable_0_2_0_rc3
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8234d 11h /or1k/tags/stable_0_2_0_rc3

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.