OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [insight/] [opcodes/] [or32.c] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5581d 13h /or1k/trunk/insight/opcodes/or32.c
1748 These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.

Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals.		 jeremybennett 5730d 19h /or1k/trunk/insight/opcodes/or32.c
1672 Store instructions don't modify any register. Don't mark them as such in the
arch. definitions		 nogj 6727d 16h /or1k/trunk/insight/opcodes/or32.c
1656 Pass the instruction operands as part of the op_queue structure. nogj 6727d 17h /or1k/trunk/insight/opcodes/or32.c
1605 Execute l.ff1 instruction nogj 6789d 18h /or1k/trunk/insight/opcodes/or32.c
1597 Fix parsing the destination register nogj 6801d 20h /or1k/trunk/insight/opcodes/or32.c
1590 Added l.fl1 lampret 6804d 17h /or1k/trunk/insight/opcodes/or32.c
1557 Fix most warnings issued by gcc4 nogj 6864d 03h /or1k/trunk/insight/opcodes/or32.c
1554 fixed l.maci encoding phoenix 6881d 14h /or1k/trunk/insight/opcodes/or32.c
1475 l.rfe does not have a delay slot. Don't mark it as such. nogj 6994d 17h /or1k/trunk/insight/opcodes/or32.c
1452 Implement a dynamic recompiler to speed up the execution nogj 7021d 20h /or1k/trunk/insight/opcodes/or32.c
1440 Reclasify l.trap and l.sys to be an exception instruction nogj 7021d 20h /or1k/trunk/insight/opcodes/or32.c
1384 Fix the parameters to the l.ff1/l.maci instructions nogj 7037d 00h /or1k/trunk/insight/opcodes/or32.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7071d 18h /or1k/trunk/insight/opcodes/or32.c
1346 Remove the global op structure nogj 7084d 22h /or1k/trunk/insight/opcodes/or32.c
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.		 nogj 7084d 22h /or1k/trunk/insight/opcodes/or32.c
1341 Mark wich operand is the destination operand in the architechture definition nogj 7084d 23h /or1k/trunk/insight/opcodes/or32.c
1338 l.ff1 instruction added andreje 7100d 20h /or1k/trunk/insight/opcodes/or32.c
1309 removed includes phoenix 7273d 16h /or1k/trunk/insight/opcodes/or32.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7276d 13h /or1k/trunk/insight/opcodes/or32.c
1295 Updated instruction set descriptions. Changed FP instructions encoding. lampret 7298d 13h /or1k/trunk/insight/opcodes/or32.c
1286 Changed desciption of the l.cust5 insns lampret 7347d 16h /or1k/trunk/insight/opcodes/or32.c
1285 Changed desciption of the l.cust5 insns lampret 7347d 16h /or1k/trunk/insight/opcodes/or32.c
1169 Added support for l.addc instruction. csanchez 7660d 16h /or1k/trunk/insight/opcodes/or32.c
1114 Added cvs log keywords lampret 7815d 08h /or1k/trunk/insight/opcodes/or32.c
1034 Fixed encoding for l.div/l.divu. lampret 7957d 09h /or1k/trunk/insight/opcodes/or32.c
879 Initial version of OpenRISC Custom Unit Compiler added markom 8022d 19h /or1k/trunk/insight/opcodes/or32.c
801 l.muli instruction added markom 8114d 23h /or1k/trunk/insight/opcodes/or32.c
722 floating point registers are obsolete; GPRs should be used instead markom 8142d 22h /or1k/trunk/insight/opcodes/or32.c
720 single floating point support added markom 8143d 02h /or1k/trunk/insight/opcodes/or32.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.