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[/] [pairing] - Rev 33

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Rev Log message Author Age Path
33 new email & English name of the author homer.xing 4472d 07h /pairing
32 changed surname: Xing -> Hsing. homer.xing 4472d 07h /pairing
31 accurate source code copyright comment header homer.xing 4472d 07h /pairing
30 LGPL header homer.xing 4482d 11h /pairing
29 default net type is wire homer.xing 4489d 08h /pairing
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 4489d 11h /pairing
27 definition for undefined wire homer.xing 4489d 11h /pairing
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 4495d 07h /pairing
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 4495d 07h /pairing
24 LGPL claim in each source hdl file homer.xing 4503d 07h /pairing
23 LGPL license text homer.xing 4503d 08h /pairing
22 Change TAB to space homer.xing 4503d 09h /pairing
21 Add detailed input data capture condition in the document homer.xing 4503d 09h /pairing
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 4504d 12h /pairing
19 Update synthesis result homer.xing 4505d 05h /pairing
18 add synthesis result homer.xing 4505d 05h /pairing
17 use logic for $f3m_mux6$ homer.xing 4505d 07h /pairing
16 Add synthesis configuration files homer.xing 4505d 10h /pairing
15 add document. ha ha ha homer.xing 4505d 11h /pairing
14 Move constraint file homer.xing 4505d 12h /pairing
13 Add document and synthesis directories homer.xing 4505d 12h /pairing
12 Simplify the interface of the core. homer.xing 4505d 12h /pairing
11 Cheers! as fast as a rocket homer.xing 4506d 08h /pairing
10 Ho ho, better circuit homer.xing 4507d 02h /pairing
9 Add constrains file for ISE homer.xing 4508d 06h /pairing
8 Finished Tate Pairing. Ha ha ha homer.xing 4508d 06h /pairing
7 Finish inversion @ f33m homer.xing 4516d 11h /pairing
6 add testbench for $f33m$. homer.xing 4517d 11h /pairing
5 rename director : verilog/ -> rtl/ homer.xing 4517d 11h /pairing
4 add testbench homer.xing 4518d 09h /pairing

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