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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 115

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Rev	Log message	Author	Age	Path
115	Added signals for WB Master B3.	tadejm	7659d 06h	/pci/tags/asyst_2/rtl/verilog
113	ifdefs moved to thier own lines, this confuses some of the tools.	simons	7666d 09h	/pci/tags/asyst_2/rtl/verilog
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7666d 14h	/pci/tags/asyst_2/rtl/verilog
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7668d 13h	/pci/tags/asyst_2/rtl/verilog
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7672d 10h	/pci/tags/asyst_2/rtl/verilog
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7677d 09h	/pci/tags/asyst_2/rtl/verilog
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7682d 19h	/pci/tags/asyst_2/rtl/verilog
94	Changed one critical PCI bus signal logic.	mihad	7729d 17h	/pci/tags/asyst_2/rtl/verilog
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7807d 14h	/pci/tags/asyst_2/rtl/verilog
86	Entered the option to disable no response counter in wb master.	mihad	7819d 12h	/pci/tags/asyst_2/rtl/verilog
83	Cleaned up the code. No functional changes.	mihad	7848d 09h	/pci/tags/asyst_2/rtl/verilog
81	Updated synchronization in top level fifo modules.	mihad	7862d 05h	/pci/tags/asyst_2/rtl/verilog
79	Updated.	mihad	7865d 10h	/pci/tags/asyst_2/rtl/verilog
78	Old files with wrong names removed.	mihad	7865d 10h	/pci/tags/asyst_2/rtl/verilog
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7865d 10h	/pci/tags/asyst_2/rtl/verilog
73	Bug fixes, testcases added.	mihad	7871d 11h	/pci/tags/asyst_2/rtl/verilog
72	* empty log message *	mihad	7918d 15h	/pci/tags/asyst_2/rtl/verilog
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7926d 06h	/pci/tags/asyst_2/rtl/verilog
69	Changed BIST signal names etc..	mihad	7963d 14h	/pci/tags/asyst_2/rtl/verilog
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7966d 23h	/pci/tags/asyst_2/rtl/verilog
67	Changed BIST signals for RAMs.	tadejm	7967d 04h	/pci/tags/asyst_2/rtl/verilog
66	Changed empty status generation in pciw_fifo_control.v	mihad	7970d 15h	/pci/tags/asyst_2/rtl/verilog
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7973d 13h	/pci/tags/asyst_2/rtl/verilog
63	Added additional testcase and changed rst name in BIST to trst	mihad	7973d 17h	/pci/tags/asyst_2/rtl/verilog
62	Added BIST signals for RAMs.	mihad	7976d 10h	/pci/tags/asyst_2/rtl/verilog
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7984d 10h	/pci/tags/asyst_2/rtl/verilog
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7984d 11h	/pci/tags/asyst_2/rtl/verilog
58	Removed all logic from asynchronous reset network	mihad	7989d 11h	/pci/tags/asyst_2/rtl/verilog
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7989d 17h	/pci/tags/asyst_2/rtl/verilog
56	Number of state bits define was removed	mihad	7990d 08h	/pci/tags/asyst_2/rtl/verilog

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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 115

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