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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog] - Rev 69

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Rev Log message Author Age Path
69 Changed BIST signal names etc.. mihad 7963d 18h /pci/tags/asyst_2/rtl/verilog
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7967d 03h /pci/tags/asyst_2/rtl/verilog
67 Changed BIST signals for RAMs. tadejm 7967d 08h /pci/tags/asyst_2/rtl/verilog
66 Changed empty status generation in pciw_fifo_control.v mihad 7970d 19h /pci/tags/asyst_2/rtl/verilog
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7973d 17h /pci/tags/asyst_2/rtl/verilog
63 Added additional testcase and changed rst name in BIST to trst mihad 7973d 21h /pci/tags/asyst_2/rtl/verilog
62 Added BIST signals for RAMs. mihad 7976d 14h /pci/tags/asyst_2/rtl/verilog
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7984d 14h /pci/tags/asyst_2/rtl/verilog
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7984d 15h /pci/tags/asyst_2/rtl/verilog
58 Removed all logic from asynchronous reset network mihad 7989d 15h /pci/tags/asyst_2/rtl/verilog
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7989d 21h /pci/tags/asyst_2/rtl/verilog
56 Number of state bits define was removed mihad 7990d 12h /pci/tags/asyst_2/rtl/verilog
55 Changed state machine encoding to true one-hot mihad 7990d 13h /pci/tags/asyst_2/rtl/verilog
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8023d 18h /pci/tags/asyst_2/rtl/verilog
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8023d 22h /pci/tags/asyst_2/rtl/verilog
50 Got rid of undef directives mihad 8026d 14h /pci/tags/asyst_2/rtl/verilog
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8026d 14h /pci/tags/asyst_2/rtl/verilog
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8026d 14h /pci/tags/asyst_2/rtl/verilog
47 Known issues repaired mihad 8026d 20h /pci/tags/asyst_2/rtl/verilog
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8031d 14h /pci/tags/asyst_2/rtl/verilog
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8032d 20h /pci/tags/asyst_2/rtl/verilog
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8177d 23h /pci/tags/asyst_2/rtl/verilog
33 Added some testcases, removed un-needed fifo signals mihad 8193d 19h /pci/tags/asyst_2/rtl/verilog
32 Added include statement that was missing and causing errors mihad 8201d 16h /pci/tags/asyst_2/rtl/verilog
26 Modified testbench and fixed some bugs mihad 8207d 15h /pci/tags/asyst_2/rtl/verilog
23 *** empty log message *** mihad 8225d 15h /pci/tags/asyst_2/rtl/verilog
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8225d 16h /pci/tags/asyst_2/rtl/verilog
19 *** empty log message *** mihad 8225d 16h /pci/tags/asyst_2/rtl/verilog
18 *** empty log message *** mihad 8225d 16h /pci/tags/asyst_2/rtl/verilog
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8344d 23h /pci/tags/asyst_2/rtl/verilog

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