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[/] [pci/] [tags/] [asyst_3/] [rtl] - Rev 94

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Rev	Log message	Author	Age	Path
94	Changed one critical PCI bus signal logic.	mihad	7732d 11h	/pci/tags/asyst_3/rtl
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7810d 08h	/pci/tags/asyst_3/rtl
86	Entered the option to disable no response counter in wb master.	mihad	7822d 06h	/pci/tags/asyst_3/rtl
83	Cleaned up the code. No functional changes.	mihad	7851d 03h	/pci/tags/asyst_3/rtl
81	Updated synchronization in top level fifo modules.	mihad	7864d 23h	/pci/tags/asyst_3/rtl
79	Updated.	mihad	7868d 04h	/pci/tags/asyst_3/rtl
78	Old files with wrong names removed.	mihad	7868d 04h	/pci/tags/asyst_3/rtl
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7868d 04h	/pci/tags/asyst_3/rtl
73	Bug fixes, testcases added.	mihad	7874d 05h	/pci/tags/asyst_3/rtl
72	* empty log message *	mihad	7921d 09h	/pci/tags/asyst_3/rtl
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7929d 01h	/pci/tags/asyst_3/rtl
69	Changed BIST signal names etc..	mihad	7966d 08h	/pci/tags/asyst_3/rtl
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7969d 18h	/pci/tags/asyst_3/rtl
67	Changed BIST signals for RAMs.	tadejm	7969d 22h	/pci/tags/asyst_3/rtl
66	Changed empty status generation in pciw_fifo_control.v	mihad	7973d 09h	/pci/tags/asyst_3/rtl
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7976d 07h	/pci/tags/asyst_3/rtl
63	Added additional testcase and changed rst name in BIST to trst	mihad	7976d 11h	/pci/tags/asyst_3/rtl
62	Added BIST signals for RAMs.	mihad	7979d 04h	/pci/tags/asyst_3/rtl
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7987d 04h	/pci/tags/asyst_3/rtl
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7987d 05h	/pci/tags/asyst_3/rtl
58	Removed all logic from asynchronous reset network	mihad	7992d 05h	/pci/tags/asyst_3/rtl
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7992d 11h	/pci/tags/asyst_3/rtl
56	Number of state bits define was removed	mihad	7993d 02h	/pci/tags/asyst_3/rtl
55	Changed state machine encoding to true one-hot	mihad	7993d 03h	/pci/tags/asyst_3/rtl
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8026d 08h	/pci/tags/asyst_3/rtl
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8026d 12h	/pci/tags/asyst_3/rtl
50	Got rid of undef directives	mihad	8029d 04h	/pci/tags/asyst_3/rtl
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8029d 04h	/pci/tags/asyst_3/rtl
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8029d 04h	/pci/tags/asyst_3/rtl
47	Known issues repaired	mihad	8029d 10h	/pci/tags/asyst_3/rtl

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[/] [pci/] [tags/] [asyst_3/] [rtl] - Rev 94

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